diff options
| author | Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> | 2020-05-18 01:11:00 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-06-24 13:11:08 +0200 |
| commit | f44bd3bcfd91cd7b1be709c9cfb0824e6a71b9b0 (patch) | |
| tree | 0cdc5ebeaab7c0fbc772a168a66f9f14c15315fc /drivers/spi/xilinx_spi.c | |
| parent | 26e62cc9713ebe728d01826e8c22c3c56f8e3bf4 (diff) | |
spi: zynq_[q]spi: Convert config's to macro's
Remove below config options and convert them to macros. They have never
been configured to different values than default one. And also it makes
sense to reduce the config_whitelist.
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_XILINX_SPI_IDLE_VAL
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/spi/xilinx_spi.c')
| -rw-r--r-- | drivers/spi/xilinx_spi.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 05768eef72..348630faf3 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -76,9 +76,7 @@ SPICR_SPE) #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS) -#ifndef CONFIG_XILINX_SPI_IDLE_VAL -#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) -#endif +#define XILINX_SPI_IDLE_VAL GENMASK(7, 0) #define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */ @@ -176,7 +174,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp, while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) && i < priv->fifo_depth) { - d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; + d = txp ? *txp++ : XILINX_SPI_IDLE_VAL; debug("spi_xfer: tx:%x ", d); /* write out and wait for processing (receive data) */ writel(d & SPIDTR_8BIT_MASK, ®s->spidtr); |