diff options
| author | Han Xu <han.xu@nxp.com> | 2023-09-13 16:15:35 -0500 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2023-10-10 10:13:51 +0800 |
| commit | 131e44c5448fb0ba9f8b6084cb848a84d729b2c5 (patch) | |
| tree | 1ad173fe065b5b2b788728a6ad7c2f5d8b3b50c1 /drivers/spi/nxp_fspi.c | |
| parent | d71e08098e4bc64d242c2e59f3e4398f31692975 (diff) | |
spi: nxp_fspi: reset the FLSHxCR1 registers
Reset the FLSHxCR1 registers to default value. ROM may set the register
value and it affects the SPI NAND normal functions.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/spi/nxp_fspi.c')
| -rw-r--r-- | drivers/spi/nxp_fspi.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 579d6bac9b..5db27f9ae2 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -927,6 +927,13 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, base + FSPI_AHBCR); + /* Reset the flashx control1 registers */ + reg = FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3); + fspi_writel(f, reg, base + FSPI_FLSHA1CR1); + fspi_writel(f, reg, base + FSPI_FLSHA2CR1); + fspi_writel(f, reg, base + FSPI_FLSHB1CR1); + fspi_writel(f, reg, base + FSPI_FLSHB2CR1); + /* AHB Read - Set lut sequence ID for all CS. */ fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); |