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| author | Tom Rini <trini@konsulko.com> | 2020-12-14 18:57:57 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-12-14 18:57:57 -0500 |
| commit | 8351a29d2df18c92d8e365cfa848218c3859f3d2 (patch) | |
| tree | 5d29001be9accfb8029df9d9ed78fba196ee07b9 /drivers/spi/cadence_qspi.h | |
| parent | ddaa94978583d07ec515e7226e397221d8cc44c8 (diff) | |
| parent | b7bbd553de0d9752f919dfc616f560f6f2504c14 (diff) | |
Merge tag 'dm-pull-14dec20' of git://git.denx.de/u-boot-dm into next
Driver model tidy-up for livetree
Driver model big rename for consistency
Python 3 clean-ups for patman
Update sandbox serial driver to use membuff
Diffstat (limited to 'drivers/spi/cadence_qspi.h')
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index ae459c74a1..64c5867609 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -15,7 +15,7 @@ #define CQSPI_DECODER_MAX_CS 16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16 -struct cadence_spi_platdata { +struct cadence_spi_plat { unsigned int ref_clk_hz; unsigned int max_hz; void *regbase; @@ -52,7 +52,7 @@ struct cadence_spi_priv { }; /* Functions call declaration */ -void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat); +void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat); void cadence_qspi_apb_controller_enable(void *reg_base_addr); void cadence_qspi_apb_controller_disable(void *reg_base_addr); void cadence_qspi_apb_dac_mode_enable(void *reg_base); @@ -62,13 +62,13 @@ int cadence_qspi_apb_command_read(void *reg_base_addr, int cadence_qspi_apb_command_write(void *reg_base_addr, const struct spi_mem_op *op); -int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat, +int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat, const struct spi_mem_op *op); -int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat, +int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat, const struct spi_mem_op *op); -int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat, +int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat, const struct spi_mem_op *op); -int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat, +int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat, const struct spi_mem_op *op); void cadence_qspi_apb_chipselect(void *reg_base, |