Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.10-rc1 v2

axi_emac:
- Change return value if RX packet is not ready

cadence_qspi:
- Enable flash reset for Versal NET

dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location

fpga:
- Add load event

mtd:
- Add missing dependency for FLASH_CFI_MTD

spi/nand:
- Minor cleanup in Xilinx drivers

versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations

watchdog:
- Use new versal-wwdt property

xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email

zynqmp_clk:
- Add handling for gem rx/tsu clocks

zynq_gem:
- Configure mdio clock at run time

zynq:
- Enable fdt overlay support

zynq_sdhci:
- Call dll reset only for ZynqMP SOCs

1 files changed, 5 insertions, 8 deletions

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 2d715e478c..cc3a54f295 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -249,17 +249,14 @@ static int cadence_spi_probe(struct udevice *bus)
 
 	priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
 
-	if (IS_ENABLED(CONFIG_ARCH_VERSAL)) {
-		/* Versal platform uses spi calibration to set read delay */
+	/* Versal and Versal-NET use spi calibration to set read delay */
+	if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
+	    CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
 		if (priv->read_delay >= 0)
 			priv->read_delay = -1;
-		/* Reset ospi flash device */
-		ret = cadence_qspi_versal_flash_reset(bus);
-		if (ret)
-			return ret;
-	}
 
-	return 0;
+	/* Reset ospi flash device */
+	return cadence_qspi_versal_flash_reset(bus);
 }
 
 static int cadence_spi_remove(struct udevice *dev)