diff options
| author | Johan Jonker <jbx6244@gmail.com> | 2023-03-13 01:32:18 +0100 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-05-06 17:28:18 +0800 |
| commit | 842fb5de424e53d097230a1d0ab6d7ba39b446c7 (patch) | |
| tree | ce78e06c1880e39d11ab5cafe33a90e7426b475e /drivers/spi/cadence_qspi.c | |
| parent | a12a73b66476c48dfe5afd2c3711153d09feda6c (diff) | |
drivers: use devfdt_get_addr_size_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index
function in the various files in the drivers directory that cast to
a pointer.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/spi/cadence_qspi.c')
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index f931e4cf3e..ac81468a18 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -390,8 +390,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) ofnode subnode; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); - plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, - &plat->ahbsize); + plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize); plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs"); plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4); |