diff options
| author | Tom Rini <trini@konsulko.com> | 2023-01-20 14:21:38 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-01-20 14:21:38 -0500 |
| commit | 0b9b01517f0b1398ec27dbb47faf3645b719e02c (patch) | |
| tree | fac11441ba4056e75d3b59811da3b0a91d1cfcf5 /drivers/ram | |
| parent | 8bd3c0a7e17ee17c771cabc0e548a1a436ac021d (diff) | |
| parent | 6333acb961b6fcaa60c6e5b623d676b332481cfa (diff) | |
Merge branch '2023-01-20-finish-CONFIG-migration-work'
- Merge in the final batch of CONFIG to Kconfig/CFG migration work. This
includes a fix for a number of ns16550 or similar UARTs due to a
migration bug. We also pull in a revert for enabling CONFIG_VIDEO on
tools-only_defconfig.
Diffstat (limited to 'drivers/ram')
| -rw-r--r-- | drivers/ram/aspeed/sdram_ast2600.c | 12 | ||||
| -rw-r--r-- | drivers/ram/octeon/octeon_ddr.c | 8 | ||||
| -rw-r--r-- | drivers/ram/rockchip/dmc-rk3368.c | 2 |
3 files changed, 11 insertions, 11 deletions
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index a2d7ca82fc..1876755412 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -104,10 +104,10 @@ * -> WL = AL + CWL + PL = CWL * -> RL = AL + CL + PL = CL */ -#define CONFIG_WL 9 -#define CONFIG_RL 12 -#define T_RDDATA_EN ((CONFIG_RL - 2) << 8) -#define T_PHY_WRLAT (CONFIG_WL - 2) +#define CFG_WL 9 +#define CFG_RL 12 +#define T_RDDATA_EN ((CFG_RL - 2) << 8) +#define T_PHY_WRLAT (CFG_WL - 2) /* MR0 */ #define MR0_CL_12 (BIT(4) | BIT(2)) @@ -974,8 +974,8 @@ static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) /* update CL and WL */ reg = readl(®s->ac_timing[1]); reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING); - reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) | - FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5); + reg |= FIELD_PREP(SDRAM_WL_SETTING, CFG_WL - 5) | + FIELD_PREP(SDRAM_CL_SETTING, CFG_RL - 5); writel(reg, ®s->ac_timing[1]); writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c index bb21078df1..ff2899d748 100644 --- a/drivers/ram/octeon/octeon_ddr.c +++ b/drivers/ram/octeon/octeon_ddr.c @@ -17,7 +17,7 @@ #include <mach/octeon_ddr.h> -#define CONFIG_REF_HERTZ 50000000 +#define CFG_REF_HERTZ 50000000 DECLARE_GLOBAL_DATA_PTR; @@ -152,7 +152,7 @@ static void cvmx_l2c_set_big_size(struct ddr_priv *priv, u64 mem_size, int mode) static u32 octeon3_refclock(u32 alt_refclk, u32 ddr_hertz, struct dimm_config *dimm_config) { - u32 ddr_ref_hertz = CONFIG_REF_HERTZ; + u32 ddr_ref_hertz = CFG_REF_HERTZ; int ddr_type; int spd_dimm_type; @@ -2453,7 +2453,7 @@ try_again: } else { if (ddr_ref_hertz == 100000000) { debug("N0: DRAM init: requested 100 MHz refclk NOT SUPPORTED\n"); - ddr_ref_hertz = CONFIG_REF_HERTZ; + ddr_ref_hertz = CFG_REF_HERTZ; } } @@ -2486,7 +2486,7 @@ try_again: if (hertz_diff > ((int)ddr_hertz * 5 / 100)) { // nope, diff is greater than than 5% debug("N0: DRAM init: requested 100 MHz refclk NOT FOUND\n"); - ddr_ref_hertz = CONFIG_REF_HERTZ; + ddr_ref_hertz = CFG_REF_HERTZ; // clear the flag before trying again!! set_ddr_clock_initialized(priv, 0, 0); goto try_again; diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 6929a7e494..dd5b191744 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -109,7 +109,7 @@ enum { PCTL_STAT_MSK = 7, INIT_MEM = 0, CONFIG, - CONFIG_REQ, + CFG_REQ, ACCESS, ACCESS_REQ, LOW_POWER, |