diff options
| author | Tom Rini <trini@konsulko.com> | 2021-01-13 15:00:53 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-01-13 15:00:53 -0500 |
| commit | ab1a425524a79eeca61e7b67fdf382c7a499346f (patch) | |
| tree | 08f3925c3cb439f674ebf41cc5003c95ea5c4a57 /drivers/phy | |
| parent | 795f8fd0b591eef7cf3f8c6fcf9788280029cc4a (diff) | |
| parent | 7ccaa31380a4abb2b23718008a54fe2917db8edf (diff) | |
Merge tag 'u-boot-stm32-20210113' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
- Activate OF_LIVE for ST stm32mp15 boards
- Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
- Correction in stm32prog command on uart: always flush DFU on start command
- Update USB-C power detection algorithm on DK boards
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/phy-stm32-usbphyc.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index f23aef4fb0..02d859a039 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -3,6 +3,8 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_PHY + #include <common.h> #include <clk.h> #include <div64.h> @@ -98,8 +100,8 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc) u32 usbphyc_pll; if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) { - pr_debug("%s: input clk freq (%dHz) out of range\n", - __func__, clk_rate); + log_debug("input clk freq (%dHz) out of range\n", + clk_rate); return -EINVAL; } @@ -116,8 +118,8 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc) writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL); - pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__, - clk_rate, pll_params.ndiv, pll_params.frac); + log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n", + clk_rate, pll_params.ndiv, pll_params.frac); return 0; } @@ -154,7 +156,7 @@ static int stm32_usbphyc_phy_init(struct phy *phy) true : false; int ret; - pr_debug("%s phy ID = %lu\n", __func__, phy->id); + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); /* Check if one phy port has already configured the pll */ if (pllen && stm32_usbphyc_is_init(usbphyc)) goto initialized; @@ -200,7 +202,7 @@ static int stm32_usbphyc_phy_exit(struct phy *phy) struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; int ret; - pr_debug("%s phy ID = %lu\n", __func__, phy->id); + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); usbphyc_phy->init = false; /* Check if other phy port requires pllen */ @@ -239,7 +241,7 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy) struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; int ret; - pr_debug("%s phy ID = %lu\n", __func__, phy->id); + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); if (usbphyc_phy->vdd) { ret = regulator_set_enable(usbphyc_phy->vdd, true); if (ret) @@ -262,7 +264,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; int ret; - pr_debug("%s phy ID = %lu\n", __func__, phy->id); + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); usbphyc_phy->powered = false; if (stm32_usbphyc_is_powered(usbphyc)) |