Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.

The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).

2 files changed, 1 insertions, 96 deletions

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 2e24d12214..b23faa228e 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -29,7 +29,6 @@
 #include <miiphy.h>
 #include <net.h>
 #include <reset.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <wait_bit.h>
 
 #define MDIO_CMD_MII_BUSY		BIT(0)
@@ -81,13 +80,6 @@
 
 #define AHB_GATE_OFFSET_EPHY	0
 
-/* IO mux settings */
-#define SUN8I_IOMUX_H3		2
-#define SUN8I_IOMUX_R40		5
-#define SUN8I_IOMUX_H6		5
-#define SUN8I_IOMUX_H616	2
-#define SUN8I_IOMUX		4
-
 /* H3/A64 EMAC Register's offset */
 #define EMAC_CTL0		0x00
 #define EMAC_CTL0_FULL_DUPLEX		BIT(0)
@@ -519,85 +511,6 @@ static int sun8i_emac_eth_start(struct udevice *dev)
 	return 0;
 }
 
-static int parse_phy_pins(struct udevice *dev)
-{
-	int offset;
-	const char *pin_name;
-	int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
-	u32 iomux;
-
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
-				       "pinctrl-0");
-	if (offset < 0) {
-		printf("WARNING: emac: cannot find pinctrl-0 node\n");
-		return offset;
-	}
-
-	drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
-					     "drive-strength", ~0);
-	if (drive != ~0) {
-		if (drive <= 10)
-			drive = SUN4I_PINCTRL_10_MA;
-		else if (drive <= 20)
-			drive = SUN4I_PINCTRL_20_MA;
-		else if (drive <= 30)
-			drive = SUN4I_PINCTRL_30_MA;
-		else
-			drive = SUN4I_PINCTRL_40_MA;
-	}
-
-	if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
-		pull = SUN4I_PINCTRL_PULL_UP;
-	else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
-		pull = SUN4I_PINCTRL_PULL_DOWN;
-
-	/*
-	 * The GPIO pinmux value is an integration choice, so depends on the
-	 * SoC, not the EMAC variant.
-	 */
-	if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
-		iomux = SUN8I_IOMUX_H3;
-	else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
-		iomux = SUN8I_IOMUX_R40;
-	else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
-		iomux = SUN8I_IOMUX_H6;
-	else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
-		iomux = SUN8I_IOMUX_H616;
-	else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
-		iomux = SUN8I_IOMUX;
-	else if (IS_ENABLED(CONFIG_MACH_SUN50I))
-		iomux = SUN8I_IOMUX;
-	else
-		BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
-
-	for (i = 0; ; i++) {
-		int pin;
-
-		pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
-					      "pins", i, NULL);
-		if (!pin_name)
-			break;
-
-		pin = sunxi_name_to_gpio(pin_name);
-		if (pin < 0)
-			continue;
-
-		sunxi_gpio_set_cfgpin(pin, iomux);
-
-		if (drive != ~0)
-			sunxi_gpio_set_drv(pin, drive);
-		if (pull != ~0)
-			sunxi_gpio_set_pull(pin, pull);
-	}
-
-	if (!i) {
-		printf("WARNING: emac: cannot find pins property\n");
-		return -2;
-	}
-
-	return 0;
-}
-
 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 {
 	struct emac_eth_dev *priv = dev_get_priv(dev);
@@ -965,9 +878,6 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
 
 	priv->interface = pdata->phy_interface;
 
-	if (!priv->use_internal_phy)
-		parse_phy_pins(dev);
-
 	sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
 						  "allwinner,tx-delay-ps", 0);
 	if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 17ad88e732..d15b0add7c 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -17,7 +17,6 @@
 #include <net.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
 
 /* EMAC register  */
 struct emac_regs {
@@ -511,15 +510,11 @@ static int sunxi_emac_board_setup(struct udevice *dev,
 	struct sunxi_sramc_regs *sram =
 		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
 	struct emac_regs *regs = priv->regs;
-	int pin, ret;
+	int ret;
 
 	/* Map SRAM to EMAC */
 	setbits_le32(&sram->ctrl1, 0x5 << 2);
 
-	/* Configure pin mux settings for MII Ethernet */
-	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
-
 	/* Set up clock gating */
 	ret = clk_enable(&priv->clk);
 	if (ret) {