Merge branch '2023-01-20-finish-CONFIG-migration-work'

- Merge in the final batch of CONFIG to Kconfig/CFG migration work. This
  includes a fix for a number of ns16550 or similar UARTs due to a
  migration bug. We also pull in a revert for enabling CONFIG_VIDEO on
  tools-only_defconfig.

17 files changed, 122 insertions, 130 deletions

diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index a16c998b2a..da1f3f4580 100644
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -143,11 +143,11 @@ enum ag7xxx_model {
 #define AG7XXX_ETH_CFG_MII_GE0			BIT(1)
 #define AG7XXX_ETH_CFG_RGMII_GE0		BIT(0)
 
-#define CONFIG_TX_DESCR_NUM	8
-#define CONFIG_RX_DESCR_NUM	8
-#define CONFIG_ETH_BUFSIZE	2048
-#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
-#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+#define CFG_TX_DESCR_NUM	8
+#define CFG_RX_DESCR_NUM	8
+#define CFG_ETH_BUFSIZE	2048
+#define TX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
 
 /* DMA descriptor. */
 struct ag7xxx_dma_desc {
@@ -162,8 +162,8 @@ struct ag7xxx_dma_desc {
 };
 
 struct ar7xxx_eth_priv {
-	struct ag7xxx_dma_desc	tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
-	struct ag7xxx_dma_desc	rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+	struct ag7xxx_dma_desc	tx_mac_descrtable[CFG_TX_DESCR_NUM];
+	struct ag7xxx_dma_desc	rx_mac_descrtable[CFG_RX_DESCR_NUM];
 	char		txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 	char		rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 
@@ -408,11 +408,11 @@ static void ag7xxx_dma_clean_tx(struct udevice *dev)
 	u32 start, end;
 	int i;
 
-	for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
+	for (i = 0; i < CFG_TX_DESCR_NUM; i++) {
 		curr = &priv->tx_mac_descrtable[i];
-		next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
+		next = &priv->tx_mac_descrtable[(i + 1) % CFG_TX_DESCR_NUM];
 
-		curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
+		curr->data_addr = virt_to_phys(&priv->txbuffs[i * CFG_ETH_BUFSIZE]);
 		curr->config = AG7XXX_DMADESC_IS_EMPTY;
 		curr->next_desc = virt_to_phys(next);
 	}
@@ -432,11 +432,11 @@ static void ag7xxx_dma_clean_rx(struct udevice *dev)
 	u32 start, end;
 	int i;
 
-	for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
+	for (i = 0; i < CFG_RX_DESCR_NUM; i++) {
 		curr = &priv->rx_mac_descrtable[i];
-		next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
+		next = &priv->rx_mac_descrtable[(i + 1) % CFG_RX_DESCR_NUM];
 
-		curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
+		curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CFG_ETH_BUFSIZE]);
 		curr->config = AG7XXX_DMADESC_IS_EMPTY;
 		curr->next_desc = virt_to_phys(next);
 	}
@@ -492,7 +492,7 @@ static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
 	       priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
 
 	/* Switch to next TX descriptor. */
-	priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
+	priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CFG_TX_DESCR_NUM;
 
 	return 0;
 }
@@ -543,7 +543,7 @@ static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
 	flush_dcache_range(start, end);
 
 	/* Switch to next RX descriptor. */
-	priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
+	priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CFG_RX_DESCR_NUM;
 
 	return 0;
 }
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ddaf7ed1d3..e09ca3313d 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -38,7 +38,7 @@ static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 	struct eth_mac_regs *mac_p = priv->mac_regs_p;
 	ulong start;
 	u16 miiaddr;
-	int timeout = CONFIG_MDIO_TIMEOUT;
+	int timeout = CFG_MDIO_TIMEOUT;
 
 	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
 		  ((reg << MIIREGSHIFT) & MII_REGMSK);
@@ -62,7 +62,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 	struct eth_mac_regs *mac_p = priv->mac_regs_p;
 	ulong start;
 	u16 miiaddr;
-	int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
+	int ret = -ETIMEDOUT, timeout = CFG_MDIO_TIMEOUT;
 
 	writel(val, &mac_p->miidata);
 	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
@@ -229,9 +229,9 @@ static void tx_descs_init(struct dw_eth_dev *priv)
 	struct dmamacdescr *desc_p;
 	u32 idx;
 
-	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+	for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
-		desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
+		desc_p->dmamac_addr = (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE];
 		desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
 
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
@@ -277,9 +277,9 @@ static void rx_descs_init(struct dw_eth_dev *priv)
 	 * GMAC data will be corrupted. */
 	flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
 
-	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+	for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
-		desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+		desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE];
 		desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
 
 		desc_p->dmamac_cntl =
@@ -377,7 +377,7 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
 
 	start = get_timer(0);
 	while (readl(&dma_p->busmode) & DMAMAC_SRST) {
-		if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
+		if (get_timer(start) >= CFG_MACRESET_TIMEOUT) {
 			printf("DMA reset timeout\n");
 			return -ETIMEDOUT;
 		}
@@ -495,7 +495,7 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
 	flush_dcache_range(desc_start, desc_end);
 
 	/* Test the wrap-around condition. */
-	if (++desc_num >= CONFIG_TX_DESCR_NUM)
+	if (++desc_num >= CFG_TX_DESCR_NUM)
 		desc_num = 0;
 
 	priv->tx_currdescnum = desc_num;
@@ -555,7 +555,7 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
 	flush_dcache_range(desc_start, desc_end);
 
 	/* Test the wrap-around condition. */
-	if (++desc_num >= CONFIG_RX_DESCR_NUM)
+	if (++desc_num >= CFG_RX_DESCR_NUM)
 		desc_num = 0;
 	priv->rx_currdescnum = desc_num;
 
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 138c3c14bf..9da4e902cb 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -14,14 +14,14 @@
 #include <asm-generic/gpio.h>
 #endif
 
-#define CONFIG_TX_DESCR_NUM	16
-#define CONFIG_RX_DESCR_NUM	16
-#define CONFIG_ETH_BUFSIZE	2048
-#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
-#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+#define CFG_TX_DESCR_NUM	16
+#define CFG_RX_DESCR_NUM	16
+#define CFG_ETH_BUFSIZE	2048
+#define TX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
 
-#define CONFIG_MACRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
-#define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
+#define CFG_MACRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
+#define CFG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
 
 struct eth_mac_regs {
 	u32 conf;		/* 0x00 */
@@ -221,8 +221,8 @@ struct dmamacdescr {
 #endif
 
 struct dw_eth_dev {
-	struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
-	struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+	struct dmamacdescr tx_mac_descrtable[CFG_TX_DESCR_NUM];
+	struct dmamacdescr rx_mac_descrtable[CFG_RX_DESCR_NUM];
 	char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 	char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index a0424505bd..38d96ab72b 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -168,14 +168,12 @@ struct descriptor {		/* A generic descriptor. */
 	unsigned char params[0];
 };
 
-#define CONFIG_SYS_CMD_EL		0x8000
-#define CONFIG_SYS_CMD_SUSPEND		0x4000
-#define CONFIG_SYS_CMD_INT		0x2000
-#define CONFIG_SYS_CMD_IAS		0x0001	/* individual address setup */
-#define CONFIG_SYS_CMD_CONFIGURE	0x0002	/* configure */
+#define CFG_SYS_CMD_SUSPEND		0x4000
+#define CFG_SYS_CMD_IAS		0x0001	/* individual address setup */
+#define CFG_SYS_CMD_CONFIGURE	0x0002	/* configure */
 
-#define CONFIG_SYS_STATUS_C		0x8000
-#define CONFIG_SYS_STATUS_OK		0x2000
+#define CFG_SYS_STATUS_C		0x8000
+#define CFG_SYS_STATUS_OK		0x2000
 
 /* Misc. */
 #define NUM_RX_DESC		PKTBUFSRX
@@ -413,7 +411,7 @@ static int eepro100_txcmd_send(struct eepro100_priv *priv,
 		invalidate_dcache_range((unsigned long)desc,
 					(unsigned long)desc + sizeof(*desc));
 		rstat = le16_to_cpu(desc->status);
-		if (rstat & CONFIG_SYS_STATUS_C)
+		if (rstat & CFG_SYS_STATUS_C)
 			break;
 
 		if (i++ >= TOUT_LOOP) {
@@ -426,7 +424,7 @@ static int eepro100_txcmd_send(struct eepro100_priv *priv,
 				(unsigned long)desc + sizeof(*desc));
 	rstat = le16_to_cpu(desc->status);
 
-	if (!(rstat & CONFIG_SYS_STATUS_OK)) {
+	if (!(rstat & CFG_SYS_STATUS_OK)) {
 		printf("TX error status = 0x%08X\n", rstat);
 		return -EIO;
 	}
@@ -579,8 +577,8 @@ static int eepro100_init_common(struct eepro100_priv *priv)
 	priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
 
 	cfg_cmd = &tx_ring[tx_cur];
-	cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
-				       CONFIG_SYS_CMD_CONFIGURE);
+	cfg_cmd->command = cpu_to_le16(CFG_SYS_CMD_SUSPEND |
+				       CFG_SYS_CMD_CONFIGURE);
 	cfg_cmd->status = 0;
 	cfg_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
 						(u32)&tx_ring[priv->tx_next]));
@@ -591,7 +589,7 @@ static int eepro100_init_common(struct eepro100_priv *priv)
 	ret = eepro100_txcmd_send(priv, cfg_cmd);
 	if (ret) {
 		if (ret == -ETIMEDOUT)
-			printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
+			printf("Error---CFG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
 		goto done;
 	}
 
@@ -600,8 +598,8 @@ static int eepro100_init_common(struct eepro100_priv *priv)
 	priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
 
 	ias_cmd = &tx_ring[tx_cur];
-	ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
-				       CONFIG_SYS_CMD_IAS);
+	ias_cmd->command = cpu_to_le16(CFG_SYS_CMD_SUSPEND |
+				       CFG_SYS_CMD_IAS);
 	ias_cmd->status = 0;
 	ias_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
 						(u32)&tx_ring[priv->tx_next]));
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ab52cc119f..006d27051e 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -59,7 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * sending and after receiving.
  */
 #ifdef CONFIG_MX28
-#define CONFIG_FEC_MXC_SWAP_PACKET
+#define CFG_FEC_MXC_SWAP_PACKET
 #endif
 
 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
@@ -76,7 +76,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #undef DEBUG
 
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CFG_FEC_MXC_SWAP_PACKET
 static void swap_packet(uint32_t *packet, int length)
 {
 	int i;
@@ -685,7 +685,7 @@ static int fecmxc_send(struct udevice *dev, void *packet, int length)
 	 * transmission, the second will be empty and only used to stop the DMA
 	 * engine. We also flush the packet to RAM here to avoid cache trouble.
 	 */
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CFG_FEC_MXC_SWAP_PACKET
 	swap_packet((uint32_t *)packet, length);
 #endif
 
@@ -875,7 +875,7 @@ static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
 			invalidate_dcache_range(addr, end);
 
 			/* Fill the buffer and pass it to upper layers */
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CFG_FEC_MXC_SWAP_PACKET
 			swap_packet((uint32_t *)addr, frame_length);
 #endif
 
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index e1fba24471..7dfa821909 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -363,7 +363,7 @@ int fm_init_common(int index, struct ccsr_fman *reg, const char *firmware_name)
 
 	if (src == BOOT_SOURCE_IFC_NOR) {
 		addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
-				CONFIG_SYS_FSL_IFC_BASE);
+				CFG_SYS_FSL_IFC_BASE);
 #ifdef CONFIG_CMD_NAND
 	} else if (src == BOOT_SOURCE_IFC_NAND) {
 		size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 48dd558405..eae2065451 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -32,11 +32,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | \
 					 (REG & 0x1f) << 18) | (VAL & 0xffff))
 
-#ifndef CONFIG_SYS_UNSPEC_PHYID
-#	define CONFIG_SYS_UNSPEC_PHYID		0
+#ifndef CFG_SYS_UNSPEC_PHYID
+#	define CFG_SYS_UNSPEC_PHYID		0
 #endif
-#ifndef CONFIG_SYS_UNSPEC_STRID
-#	define CONFIG_SYS_UNSPEC_STRID		0
+#ifndef CFG_SYS_UNSPEC_STRID
+#	define CFG_SYS_UNSPEC_STRID		0
 #endif
 
 typedef struct phy_info_struct {
@@ -58,8 +58,8 @@ phy_info_t phyinfo[] = {
 	{0x20005C90, "N83848"},		/* National 83848 */
 	{0x20005CA2, "N83849"},		/* National 83849 */
 	{0x01814400, "QS6612"},		/* QS6612 */
-#if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID)
-	{CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID},
+#if defined(CFG_SYS_UNSPEC_PHYID) && defined(CFG_SYS_UNSPEC_STRID)
+	{CFG_SYS_UNSPEC_PHYID, CFG_SYS_UNSPEC_STRID},
 #endif
 	{0, 0}
 };
diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c
index 50d066a8ba..0a9bdb3ddb 100644
--- a/drivers/net/mt7628-eth.c
+++ b/drivers/net/mt7628-eth.c
@@ -127,9 +127,9 @@ struct fe_tx_dma {
 
 #define MTK_QDMA_PAGE_SIZE	2048
 
-#define CONFIG_MDIO_TIMEOUT	100
-#define CONFIG_DMA_STOP_TIMEOUT	100
-#define CONFIG_TX_DMA_TIMEOUT	100
+#define CFG_MDIO_TIMEOUT	100
+#define CFG_DMA_STOP_TIMEOUT	100
+#define CFG_TX_DMA_TIMEOUT	100
 
 struct mt7628_eth_dev {
 	void __iomem *base;		/* frame engine base address */
@@ -162,7 +162,7 @@ static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set)
 	int ret;
 
 	ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set,
-				CONFIG_MDIO_TIMEOUT, false);
+				CFG_MDIO_TIMEOUT, false);
 	if (ret) {
 		printf("MDIO operation timeout!\n");
 		return -ETIMEDOUT;
@@ -352,7 +352,7 @@ static void eth_dma_stop(struct mt7628_eth_dev *priv)
 	/* Wait for DMA to stop */
 	ret = wait_for_bit_le32(base + PDMA_GLO_CFG,
 				RX_DMA_BUSY | TX_DMA_BUSY, false,
-				CONFIG_DMA_STOP_TIMEOUT, false);
+				CFG_DMA_STOP_TIMEOUT, false);
 	if (ret)
 		printf("DMA stop timeout error!\n");
 }
@@ -399,7 +399,7 @@ static int mt7628_eth_send(struct udevice *dev, void *packet, int length)
 
 	/* Check if buffer is ready for next TX DMA */
 	ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true,
-				CONFIG_TX_DMA_TIMEOUT, false);
+				CFG_TX_DMA_TIMEOUT, false);
 	if (ret) {
 		printf("TX: DMA still busy on buffer %d\n", idx);
 		return ret;
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 8c9afdf79a..1bad50d344 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -66,8 +66,6 @@ do {									\
 
 #define NET_SKB_PAD	max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
 
-#define CONFIG_NR_CPUS		1
-
 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
 #define WRAP			(2 + ETH_HLEN + 4 + 32)
 #define MTU			1500
@@ -589,7 +587,7 @@ enum mv_netc_lanes {
 
 /* Default number of RXQs in use */
 #define MVPP2_DEFAULT_RXQ		1
-#define CONFIG_MV_ETH_RXQ		8	/* increment by 8 */
+#define CFG_MV_ETH_RXQ		8	/* increment by 8 */
 
 /* Max number of Rx descriptors */
 #define MVPP2_MAX_RXD			16
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index 1e52917ff2..151bc55e07 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -11,11 +11,11 @@
 #include <stdio_dev.h>
 #include <net.h>
 
-#ifndef CONFIG_NETCONSOLE_BUFFER_SIZE
-#define CONFIG_NETCONSOLE_BUFFER_SIZE 512
+#ifndef CFG_NETCONSOLE_BUFFER_SIZE
+#define CFG_NETCONSOLE_BUFFER_SIZE 512
 #endif
 
-static char input_buffer[CONFIG_NETCONSOLE_BUFFER_SIZE];
+static char input_buffer[CFG_NETCONSOLE_BUFFER_SIZE];
 static int input_size; /* char count in input buffer */
 static int input_offset; /* offset to valid chars in input buffer */
 static int input_recursion;
diff --git a/drivers/net/npcm750_eth.c b/drivers/net/npcm750_eth.c
index bd29a10def..2028f4ae28 100644
--- a/drivers/net/npcm750_eth.c
+++ b/drivers/net/npcm750_eth.c
@@ -18,15 +18,15 @@
 #include <linux/iopoll.h>
 
 #define MAC_ADDR_SIZE		6
-#define CONFIG_TX_DESCR_NUM	32
-#define CONFIG_RX_DESCR_NUM	32
+#define CFG_TX_DESCR_NUM	32
+#define CFG_RX_DESCR_NUM	32
 
 #define TX_TOTAL_BUFSIZE	\
-		((CONFIG_TX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
+		((CFG_TX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
 #define RX_TOTAL_BUFSIZE	\
-		((CONFIG_RX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
+		((CFG_RX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
 
-#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
 
 struct npcm750_rxbd {
 	unsigned int sl;
@@ -101,8 +101,8 @@ struct emc_regs {
 };
 
 struct npcm750_eth_dev {
-	struct npcm750_txbd tdesc[CONFIG_TX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
-	struct npcm750_rxbd rdesc[CONFIG_RX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
+	struct npcm750_txbd tdesc[CFG_TX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
+	struct npcm750_rxbd rdesc[CFG_RX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
 	u8 txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 	u8 rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 	struct emc_regs *emc_regs_p;
@@ -279,7 +279,7 @@ static int npcm750_mdio_read(struct mii_dev *bus, int addr, int devad, int regs)
 	struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
 	struct emc_regs *reg = priv->emc_regs_p;
 	u32 start, val;
-	int timeout = CONFIG_MDIO_TIMEOUT;
+	int timeout = CFG_MDIO_TIMEOUT;
 
 	val = (addr << 0x08) | regs | PHYBUSY | (MIIDA_MDCCR_60 << 20);
 	writel(val, &reg->miida);
@@ -301,7 +301,7 @@ static int npcm750_mdio_write(struct mii_dev *bus, int addr, int devad, int regs
 	struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
 	struct emc_regs *reg = priv->emc_regs_p;
 	ulong start;
-	int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
+	int ret = -ETIMEDOUT, timeout = CFG_MDIO_TIMEOUT;
 
 	writel(val, &reg->miid);
 	writel((addr << 0x08) | regs | PHYBUSY | PHYWR | (MIIDA_MDCCR_60 << 20), &reg->miida);
@@ -354,19 +354,19 @@ static void npcm750_tx_descs_init(struct npcm750_eth_dev *priv)
 	writel((u32)desc_table_p, &reg->txdlsa);
 	priv->curr_txd = desc_table_p;
 
-	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+	for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
 		desc_p->buffer = (u32)&txbuffs[idx * PKTSIZE_ALIGN];
 		desc_p->sl = 0;
 		desc_p->mode = 0;
 		desc_p->mode = TX_OWEN_CPU | PADDINGMODE | CRCMODE | MACTXINTEN;
-		if (idx < (CONFIG_TX_DESCR_NUM - 1))
+		if (idx < (CFG_TX_DESCR_NUM - 1))
 			desc_p->next = (u32)&desc_table_p[idx + 1];
 		else
 			desc_p->next = (u32)&priv->tdesc[0];
 	}
 	flush_dcache_range((ulong)&desc_table_p[0],
-			   (ulong)&desc_table_p[CONFIG_TX_DESCR_NUM]);
+			   (ulong)&desc_table_p[CFG_TX_DESCR_NUM]);
 }
 
 static void npcm750_rx_descs_init(struct npcm750_eth_dev *priv)
@@ -378,22 +378,22 @@ static void npcm750_rx_descs_init(struct npcm750_eth_dev *priv)
 	u32 idx;
 
 	flush_dcache_range((ulong)priv->rxbuffs[0],
-			   (ulong)priv->rxbuffs[CONFIG_RX_DESCR_NUM]);
+			   (ulong)priv->rxbuffs[CFG_RX_DESCR_NUM]);
 
 	writel((u32)desc_table_p, &reg->rxdlsa);
 	priv->curr_rxd = desc_table_p;
 
-	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+	for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
 		desc_p->sl = RX_OWEN_DMA;
 		desc_p->buffer = (u32)&rxbuffs[idx * PKTSIZE_ALIGN];
-		if (idx < (CONFIG_RX_DESCR_NUM - 1))
+		if (idx < (CFG_RX_DESCR_NUM - 1))
 			desc_p->next = (u32)&desc_table_p[idx + 1];
 		else
 			desc_p->next = (u32)&priv->rdesc[0];
 	}
 	flush_dcache_range((ulong)&desc_table_p[0],
-			   (ulong)&desc_table_p[CONFIG_RX_DESCR_NUM]);
+			   (ulong)&desc_table_p[CFG_RX_DESCR_NUM]);
 }
 
 static void npcm750_set_fifo_threshold(struct npcm750_eth_dev *priv)
diff --git a/drivers/net/octeon/octeon_eth.c b/drivers/net/octeon/octeon_eth.c
index fbb1afc08a..659ba51ecb 100644
--- a/drivers/net/octeon/octeon_eth.c
+++ b/drivers/net/octeon/octeon_eth.c
@@ -58,7 +58,7 @@
 #include <mach/cvmx-mdio.h>
 
 /** Maximum receive packet size (hardware default is 1536) */
-#define CONFIG_OCTEON_NETWORK_MRU 1536
+#define CFG_OCTEON_NETWORK_MRU 1536
 
 #define OCTEON_BOOTLOADER_NAMED_BLOCK_TMP_PREFIX "__tmp"
 
@@ -199,7 +199,7 @@ static void cvm_oct_fill_hw_memory(u64 pool, u64 size, u64 elements)
  */
 static void cvm_oct_configure_common_hw(void)
 {
-	int mru = env_get_ulong("octeon_mru", 0, CONFIG_OCTEON_NETWORK_MRU);
+	int mru = env_get_ulong("octeon_mru", 0, CFG_OCTEON_NETWORK_MRU);
 	int packet_pool_size = CVMX_FPA_PACKET_POOL_SIZE;
 
 	if (mru > packet_pool_size)
@@ -224,7 +224,7 @@ static void cvm_oct_configure_common_hw(void)
 	cvmx_helper_initialize_packet_io_local();
 
 	/* The MRU defaults to 1536 bytes by the hardware.  Setting
-	 * CONFIG_OCTEON_NETWORK_MRU allows this to be overridden.
+	 * CFG_OCTEON_NETWORK_MRU allows this to be overridden.
 	 */
 	if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
 		struct cvmx_pki_global_config gbl_cfg;
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 580ac8e8fb..5eaff053a0 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -62,6 +62,10 @@ config MV88E61XX_PHY_PORTS
 
 config MV88E61XX_FIXED_PORTS
 	hex "Bitmask of PHYless serdes Ports"
+	default 0x0
+	help
+	  These are ports without PHYs that may be wired directly to other
+	  serdes interfaces
 
 endif # MV88E61XX_SWITCH
 
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 7eff37b244..7ab60164c7 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -167,14 +167,6 @@
 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
 #endif
 
-/*
- *  These are ports without PHYs that may be wired directly
- * to other serdes interfaces
- */
-#ifndef CONFIG_MV88E61XX_FIXED_PORTS
-#define CONFIG_MV88E61XX_FIXED_PORTS 0
-#endif
-
 /* ID register values for different switch models */
 #define PORT_SWITCH_ID_6020		0x0200
 #define PORT_SWITCH_ID_6070		0x0700
diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c
index 8fec1c21e1..6d1509d90c 100644
--- a/drivers/net/qe/dm_qe_uec.c
+++ b/drivers/net/qe/dm_qe_uec.c
@@ -20,8 +20,8 @@
 #define QE_UEC_DRIVER_NAME	"ucc_geth"
 
 /* Default UTBIPAR SMI address */
-#ifndef CONFIG_UTBIPAR_INIT_TBIPA
-#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
+#ifndef CFG_UTBIPAR_INIT_TBIPA
+#define CFG_UTBIPAR_INIT_TBIPA 0x1F
 #endif
 
 static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
@@ -840,10 +840,10 @@ static int uec_startup(struct udevice *dev)
 	utbipar = in_be32(&uec_regs->utbipar);
 	utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
 
-	/* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
+	/* Initialize UTBIPAR address to CFG_UTBIPAR_INIT_TBIPA for ALL UEC.
 	 * This frees up the remaining SMI addresses for use.
 	 */
-	utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
+	utbipar |= CFG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
 	out_be32(&uec_regs->utbipar, utbipar);
 
 	/* Allocate Tx BDs */
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 9cca8fa4e0..e800a326b8 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -43,19 +43,19 @@
 #define MDIO_CMD_MII_CLK_CSR_DIV_128	0x3
 #define MDIO_CMD_MII_CLK_CSR_SHIFT	20
 
-#define CONFIG_TX_DESCR_NUM	32
-#define CONFIG_RX_DESCR_NUM	32
-#define CONFIG_ETH_BUFSIZE	2048 /* Note must be dma aligned */
+#define CFG_TX_DESCR_NUM	32
+#define CFG_RX_DESCR_NUM	32
+#define CFG_ETH_BUFSIZE	2048 /* Note must be dma aligned */
 
 /*
  * The datasheet says that each descriptor can transfers up to 4096 bytes
  * But later, the register documentation reduces that value to 2048,
  * using 2048 cause strange behaviours and even BSP driver use 2047
  */
-#define CONFIG_ETH_RXSIZE	2044 /* Note must fit in ETH_BUFSIZE */
+#define CFG_ETH_RXSIZE	2044 /* Note must fit in ETH_BUFSIZE */
 
-#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
-#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+#define TX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
 
 #define H3_EPHY_DEFAULT_VALUE	0x58000
 #define H3_EPHY_DEFAULT_MASK	GENMASK(31, 15)
@@ -75,7 +75,7 @@
 #define SC_ERXDC_MASK		GENMASK(9, 5)
 #define SC_ERXDC_OFFSET		5
 
-#define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
+#define CFG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
 
 #define AHB_GATE_OFFSET_EPHY	0
 
@@ -143,8 +143,8 @@ struct emac_dma_desc {
 } __aligned(ARCH_DMA_MINALIGN);
 
 struct emac_eth_dev {
-	struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
-	struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
+	struct emac_dma_desc rx_chain[CFG_TX_DESCR_NUM];
+	struct emac_dma_desc tx_chain[CFG_RX_DESCR_NUM];
 	char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 	char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 
@@ -209,7 +209,7 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 
 	ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
 				MDIO_CMD_MII_BUSY, false,
-				CONFIG_MDIO_TIMEOUT, true);
+				CFG_MDIO_TIMEOUT, true);
 	if (ret < 0)
 		return ret;
 
@@ -244,7 +244,7 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 
 	return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
 				 MDIO_CMD_MII_BUSY, false,
-				 CONFIG_MDIO_TIMEOUT, true);
+				 CFG_MDIO_TIMEOUT, true);
 }
 
 static int sun8i_eth_write_hwaddr(struct udevice *dev)
@@ -412,11 +412,11 @@ static void rx_descs_init(struct emac_eth_dev *priv)
 	invalidate_dcache_range((uintptr_t)rxbuffs,
 				(uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
 
-	for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
+	for (i = 0; i < CFG_RX_DESCR_NUM; i++) {
 		desc_p = &desc_table_p[i];
-		desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
+		desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CFG_ETH_BUFSIZE];
 		desc_p->next = (uintptr_t)&desc_table_p[i + 1];
-		desc_p->ctl_size = CONFIG_ETH_RXSIZE;
+		desc_p->ctl_size = CFG_ETH_RXSIZE;
 		desc_p->status = EMAC_DESC_OWN_DMA;
 	}
 
@@ -438,9 +438,9 @@ static void tx_descs_init(struct emac_eth_dev *priv)
 	struct emac_dma_desc *desc_p;
 	int i;
 
-	for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
+	for (i = 0; i < CFG_TX_DESCR_NUM; i++) {
 		desc_p = &desc_table_p[i];
-		desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
+		desc_p->buf_addr = (uintptr_t)&txbuffs[i * CFG_ETH_BUFSIZE];
 		desc_p->next = (uintptr_t)&desc_table_p[i + 1];
 		desc_p->ctl_size = 0;
 		desc_p->status = 0;
@@ -541,7 +541,7 @@ static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 		return 0;
 	}
 
-	if (length > CONFIG_ETH_RXSIZE) {
+	if (length > CFG_ETH_RXSIZE) {
 		debug("RX: Too large packet (%d bytes)\n", length);
 		return 0;
 	}
@@ -575,7 +575,7 @@ static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
 	cache_clean_descriptor(desc_p);
 
 	/* Move to next Descriptor and wrap around */
-	if (++desc_num >= CONFIG_TX_DESCR_NUM)
+	if (++desc_num >= CFG_TX_DESCR_NUM)
 		desc_num = 0;
 	priv->tx_currdescnum = desc_num;
 
@@ -701,7 +701,7 @@ static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
 	cache_clean_descriptor(desc_p);
 
 	/* Move to next desc and wrap-around condition. */
-	if (++desc_num >= CONFIG_RX_DESCR_NUM)
+	if (++desc_num >= CFG_RX_DESCR_NUM)
 		desc_num = 0;
 	priv->rx_currdescnum = desc_num;
 
diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c
index 2dfadbd82d..29d2fc9b54 100644
--- a/drivers/net/ti/davinci_emac.c
+++ b/drivers/net/ti/davinci_emac.c
@@ -65,8 +65,8 @@ static inline unsigned long HW_TO_BD(unsigned long x)
 #define emac_gigabit_enable(phy_addr)	/* no gigabit to enable */
 #endif
 
-#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
-#define CONFIG_SYS_EMAC_TI_CLKDIV	((EMAC_MDIO_BUS_FREQ / \
+#if !defined(CFG_SYS_EMAC_TI_CLKDIV)
+#define CFG_SYS_EMAC_TI_CLKDIV	((EMAC_MDIO_BUS_FREQ / \
 		EMAC_MDIO_CLOCK_FREQ) - 1)
 #endif
 
@@ -98,17 +98,17 @@ static int			emac_rx_queue_active = 0;
 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
 				__aligned(ARCH_DMA_MINALIGN);
 
-#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
-#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT	3
+#ifndef CFG_SYS_DAVINCI_EMAC_PHY_COUNT
+#define CFG_SYS_DAVINCI_EMAC_PHY_COUNT	3
 #endif
 
 /* PHY address for a discovered PHY (0xff - not found) */
-static u_int8_t	active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
+static u_int8_t	active_phy_addr[CFG_SYS_DAVINCI_EMAC_PHY_COUNT];
 
 /* number of PHY found active */
 static u_int8_t	num_phy;
 
-phy_t				phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
+phy_t				phy[CFG_SYS_DAVINCI_EMAC_PHY_COUNT];
 
 static int davinci_emac_write_hwaddr(struct udevice *dev)
 {
@@ -152,7 +152,7 @@ static void davinci_eth_mdio_enable(void)
 {
 	u_int32_t	clkdiv;
 
-	clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
+	clkdiv = CFG_SYS_EMAC_TI_CLKDIV;
 
 	writel((clkdiv & 0xff) |
 	       MDIO_CONTROL_ENABLE |
@@ -176,7 +176,7 @@ static int davinci_eth_phy_detect(void)
 	int		j;
 	unsigned int	count = 0;
 
-	for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
+	for (i = 0; i < CFG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
 		active_phy_addr[i] = 0xff;
 
 	udelay(1000);
@@ -190,7 +190,7 @@ static int davinci_eth_phy_detect(void)
 	for (i = 0, j = 0; i < 32; i++)
 		if (phy_act_state & (1 << i)) {
 			count++;
-			if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
+			if (count <= CFG_SYS_DAVINCI_EMAC_PHY_COUNT) {
 				active_phy_addr[j++] = i;
 			} else {
 				printf("%s: to many PHYs detected.\n",
@@ -501,7 +501,7 @@ static int davinci_emac_start(struct udevice *dev)
 	writel(1, &adap_emac->RXUNICASTSET);
 
 	/* Init MDIO & get link state */
-	clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
+	clkdiv = CFG_SYS_EMAC_TI_CLKDIV;
 	writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
 	       &adap_mdio->CONTROL);