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authorNeil Armstrong <narmstrong@baylibre.com>2020-11-11 08:22:10 +0900
committerNeil Armstrong <narmstrong@baylibre.com>2020-11-12 14:31:29 +0100
commit0dbb54eb3257c243c7968f967a6b183b1edb56c8 (patch)
tree7786695e0f7da4af96b0728c540b02c305ff4baa /drivers/mmc/meson_gx_mmc.h
parent77863d43eb2b40319619bbb4f781270d8f027189 (diff)
mmc: meson-gx: change clock phase value on SM1 SoCs
Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's working fine over 50MHz on Amlogic SM1 SoCs. Since Other Amlogic SoCs doens't report an issue, phase value is using to 180' by default. To distinguish which value is used adds an u-boot only sm1 compatible. In future, it needs to find what value is a proper about each SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
Diffstat (limited to 'drivers/mmc/meson_gx_mmc.h')
-rw-r--r--drivers/mmc/meson_gx_mmc.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h
index b4544b5562..92aec5329f 100644
--- a/drivers/mmc/meson_gx_mmc.h
+++ b/drivers/mmc/meson_gx_mmc.h
@@ -9,6 +9,11 @@
#include <mmc.h>
#include <linux/bitops.h>
+enum meson_gx_mmc_compatible {
+ MMC_COMPATIBLE_GX,
+ MMC_COMPATIBLE_SM1,
+};
+
#define SDIO_PORT_A 0
#define SDIO_PORT_B 1
#define SDIO_PORT_C 2