diff options
| author | Tom Rini <trini@konsulko.com> | 2022-12-04 10:03:57 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-23 10:09:42 -0500 |
| commit | 72fc26450493335ae191afdfcbbbb328b1df6b4d (patch) | |
| tree | 0f1bd302e911b1d41aeb900ce2178066f0ae80c6 /drivers/fpga/virtex2.c | |
| parent | 452e33efa8c98c5fa3bb11d1a8b66966df253cdc (diff) | |
global: Migrate CONFIG_FPGA_DELAY to CFG
Perform a simple rename of CONFIG_FPGA_DELAY to CFG_FPGA_DELAY
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/fpga/virtex2.c')
| -rw-r--r-- | drivers/fpga/virtex2.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index ed2a4163f6..fc99a5f483 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -22,13 +22,13 @@ /* * If the SelectMap interface can be overrun by the processor, enable - * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CONFIG_FPGA_DELAY in the board + * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board * configuration file and add board-specific support for checking BUSY status. * By default, assume that the SelectMap interface cannot be overrun. */ -#ifndef CONFIG_FPGA_DELAY -#define CONFIG_FPGA_DELAY() +#ifndef CFG_FPGA_DELAY +#define CFG_FPGA_DELAY() #endif /* @@ -196,7 +196,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) } while (!(*fn->init)(cookie)); (*fn->pgm)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (fn->clk) (*fn->clk)(true, true, cookie); @@ -205,7 +205,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) */ ts = get_timer(0); do { - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); @@ -233,7 +233,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, /* * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. */ - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (fn->cs) (*fn->cs)(false, true, cookie); if (fn->wr) @@ -269,9 +269,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, (*fn->wbulkdata)(&dummy, 1, true, cookie); } else { (*fn->wdata)(0xff, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); } } @@ -335,13 +335,13 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif (*fn->wdata)(data[bytecount++], true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); /* * Cycle the clock pin */ (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); #ifdef CONFIG_SYS_FPGA_CHECK_BUSY @@ -472,9 +472,9 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) for (bit = 7; bit >= 0; --bit) { unsigned char curr_bit = (curr_data >> bit) & 1; (*fn->wdata)(curr_bit, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); } |