diff options
| author | Ye Li <ye.li@nxp.com> | 2023-01-31 16:42:25 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-03-29 20:15:42 +0200 |
| commit | f2940f3e80beb11e9e0c317e5b748ec0c92b116f (patch) | |
| tree | f8e39f63fbd8bbee6ec9e5ee245623cfb51c039e /drivers/ddr | |
| parent | cf35290258e7c4f3893fa3a49120f2051209cfbb (diff) | |
imx: imx8ulp: Update clocks to meet max rate restrictions
Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency
restrictions. Detail clock rate changes in the patch:
PLL3 PFD2: 389M -> 324M
PLL3 PFD3: 336M -> 389M
PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD)
PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD)
PLL4 PFD0: 792M -> 594M
PLL4 PFD2: 792M -> 316.8M
NIC_AP: 96M (ND) -> 192M, 48M (LD) -> 96M
NIC_LPAV: 198 (ND) -> 192M, 99M (LD) -> 96M
USDHC0: PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD)
USDHC1: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
USDHC2: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr')
0 files changed, 0 insertions, 0 deletions