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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2023-11-16 20:46:12 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-12-06 16:05:39 +0800 |
| commit | d1b24a61404a2073034dc53a10c64434d706d998 (patch) | |
| tree | d42609575bbca8c5d1f708a42051fcf459b62d53 /drivers/ddr | |
| parent | 3980baa41144b979da784cc83d9d3cc9126ca8c6 (diff) | |
riscv: andes: Fix enable register settings of PLICSW
On 32-core platform, hart31 gets stuck at secondary_hart_loop
as the corresponding enable bit is not set in enable_ipi().
We should program the next word (0x2f84) which is assigned
as the enable register of hart31. It should be done in the same
way when we invoke riscv_send_ipi() to trigger software interrupt
on hart31.
The following diagram shows the enable bits of the fixed PLICSW
scheme.
Pending regs: 0x1000 x---0---0---0---0------0---0
Pending hart ID: 0 1 2 3 ... 30 31
Interrupt ID: 0 1 2 3 4 ... 31 32
| | | | | | |
Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0
| | | | | | |
0x2080 x---0---1---0---0-...--0---0---> hart1
| | | | | | |
0x2100 x---0---0---1---0-...--0---0---> hart2
| | | | | | |
0x2180 x---0---0---0---1-...--0---0---> hart3
. . . . . . .
. . . . . . .
. . . . . . .
0x2f00 x---0---0---0---0-...--1---0---> hart30
| | | | | | |
0x2f80 x---0---0---0---0-...--0---1---> hart31
<-------- word 0 -------><--- word 1 --->
This patch includes some cleanups to macros/functions.
Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy")
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
Diffstat (limited to 'drivers/ddr')
0 files changed, 0 insertions, 0 deletions