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| author | Priyanka Singh <priyanka.singh@nxp.com> | 2021-08-19 11:39:02 +0530 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2021-11-09 14:43:24 +0530 |
| commit | f5a37b02b0830f984518f2348ad6f3784516f130 (patch) | |
| tree | ff3824fa18f66cc6096f6491a5abe2adca316a6d /drivers/ddr/microchip/ddr2_timing.h | |
| parent | a1932ece70e1441b169650d475d7814920a94c27 (diff) | |
drivers: ddr: fsl_ddr_gen4.c: Fix divide by zero issue
Fix possible divide by zero issue in fsl_ddr_set_memctl_regs
by adding an if check
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions