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authorMarek Vasut <marex@denx.de>2022-02-26 04:37:42 +0100
committerStefano Babic <sbabic@denx.de>2022-04-12 15:36:17 +0200
commitb8a24e07b2bc8648277cb0ca8f6fb814e1e5fdb4 (patch)
tree32299442a7e36a745484be921dc0f06856f73acc /drivers/ddr/microchip/ddr2_timing.h
parent4ca42af8f5b6be986aa9c6b6b87b96a169eb9e77 (diff)
imx8m: ddrphy_utils: Add 3732 MT/s mode
Add entry for 3732 MT/s mode of operation of the LPDDR4, in which case the DDR PLL has to be configured in 933 MHz mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions