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| author | Pali Rohár <pali@kernel.org> | 2023-03-29 21:03:34 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2023-03-30 07:05:20 +0200 |
| commit | 3ac1a064e735a940c05089dee6b86377c65fa890 (patch) | |
| tree | 4496db1ec5c900837d8213a1c109139b00838ce0 /drivers/ddr/microchip/ddr2_timing.h | |
| parent | 4f67eba7331025029b22d66f2f1c7e2632ac61c3 (diff) | |
arm: mvebu: Define all BOOTROM_ERR_MODE_* macros
A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value,
which represents in which state BootROM currently is. BootROM fills one
of the possible values: 0x2 (CPU initialization), 0x3 (UART detection),
0x6 (UART booting), 0x8 (PCI Express booting), 0x9 (parallel or SPI NOR
booting), 0xA (parallel or SPI NAND booting), 0xB (SATA booting) and 0xE
(SD / eMMC booting).
Meaning of these values matches TRACE_* macros from Marvell soc_spec.h file:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2013.01-armada-18.06/tools/marvell/doimage_mv/soc_spec.h
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions