diff options
| author | Ye Li <ye.li@nxp.com> | 2023-01-31 16:42:21 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-03-29 20:15:42 +0200 |
| commit | 4e08a510d23e2e23c8a776ccea582d0acd75fd4d (patch) | |
| tree | 531df17303054600555777b003d5c86ac86f3295 /drivers/ddr/microchip/ddr2.c | |
| parent | e01d1b1e302f77bdad6d1f0c7a17c4edee1e7ebd (diff) | |
imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2.c')
0 files changed, 0 insertions, 0 deletions