diff options
| author | Chunfeng Yun <chunfeng.yun@mediatek.com> | 2023-02-17 17:04:09 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2023-03-02 22:43:43 +0100 |
| commit | 39b854ae8609306986bc8e9d7330f64be3e54829 (patch) | |
| tree | e22fa3543511612a40fa03976f83d4c2440f6625 /drivers/ddr/marvell/axp/ddr3_sdram.c | |
| parent | 5241fc8dbf2680a237ab80b6d77963f57713ba44 (diff) | |
phy: phy-mtk-tphy: add support mt8195
The T-PHY controller is designed to use use PLL integer mode, but
in fact use fractional mode for some ones on mt8195 by mistake,
this causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve signal
quality.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_sdram.c')
0 files changed, 0 insertions, 0 deletions