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| author | Tom Rini <trini@konsulko.com> | 2018-12-09 08:40:49 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-12-09 08:40:49 -0500 |
| commit | 8cb8c0c6a83bef319023ac2e967a85e1e92e18bc (patch) | |
| tree | e76bc8071eab1a08ad92f30cc4ea4ad92597fb42 /drivers/ddr/marvell/a38x/xor.c | |
| parent | 51c2345bd24837f9f67f16268da6dc71573f1325 (diff) | |
| parent | 5ca84c6dd2b3060471171cce3f76d8af35060c0b (diff) | |
Merge git://git.denx.de/u-boot-marvell
- Sync DDR training with Marvell code for Armada 38x by Chris
- Misc updates to Armada 38x Helios4 board by Aditya
Diffstat (limited to 'drivers/ddr/marvell/a38x/xor.c')
| -rw-r--r-- | drivers/ddr/marvell/a38x/xor.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c index f859596d89..5fb9e216d3 100644 --- a/drivers/ddr/marvell/a38x/xor.c +++ b/drivers/ddr/marvell/a38x/xor.c @@ -4,6 +4,7 @@ */ #include "ddr3_init.h" +#include "mv_ddr_common.h" #include "xor_regs.h" /* defines */ @@ -339,16 +340,17 @@ void ddr3_new_tip_ecc_scrub(void) { u32 cs_c, max_cs; u32 cs_ena = 0; - u32 dev_num = 0; uint64_t total_mem_size, cs_mem_size = 0; printf("DDR Training Sequence - Start scrubbing\n"); - max_cs = ddr3_tip_max_cs_get(dev_num); + max_cs = mv_ddr_cs_num_get(); for (cs_c = 0; cs_c < max_cs; cs_c++) cs_ena |= 1 << cs_c; - /* assume that all CS have same size */ +#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) + /* all chip-selects are of same size */ ddr3_calc_mem_cs_size(0, &cs_mem_size); +#endif mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); total_mem_size = max_cs * cs_mem_size; |