diff options
| author | Tom Rini <trini@konsulko.com> | 2018-12-09 08:40:49 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-12-09 08:40:49 -0500 |
| commit | 8cb8c0c6a83bef319023ac2e967a85e1e92e18bc (patch) | |
| tree | e76bc8071eab1a08ad92f30cc4ea4ad92597fb42 /drivers/ddr/marvell/a38x/mv_ddr_plat.h | |
| parent | 51c2345bd24837f9f67f16268da6dc71573f1325 (diff) | |
| parent | 5ca84c6dd2b3060471171cce3f76d8af35060c0b (diff) | |
Merge git://git.denx.de/u-boot-marvell
- Sync DDR training with Marvell code for Armada 38x by Chris
- Misc updates to Armada 38x Helios4 board by Aditya
Diffstat (limited to 'drivers/ddr/marvell/a38x/mv_ddr_plat.h')
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_plat.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h index 9c5fdecd93..a307b67976 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h @@ -1,11 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) Marvell International Ltd. and its affiliates - */ - #ifndef _MV_DDR_PLAT_H #define _MV_DDR_PLAT_H +#define MAX_DEVICE_NUM 1 #define MAX_INTERFACE_NUM 1 #define MAX_BUS_NUM 5 #define DDR_IF_CTRL_SUBPHYS_NUM 3 @@ -121,6 +117,9 @@ #define DLB_QUEUE_MAP_REG 0x1784 #define DLB_SPLIT_REG 0x1788 +/* ck swap control subphy number */ +#define CK_SWAP_CTRL_PHY_NUM 2 + /* Subphy result control per byte registers */ #define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830 #define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834 @@ -221,7 +220,7 @@ extern u16 odt_intercept[]; int mv_ddr_pre_training_soc_config(const char *ddr_type); int mv_ddr_post_training_soc_config(const char *ddr_type); void mv_ddr_mem_scrubbing(void); - +u32 mv_ddr_init_freq_get(void); void mv_ddr_odpg_enable(void); void mv_ddr_odpg_disable(void); void mv_ddr_odpg_done_clr(void); @@ -233,4 +232,5 @@ int mv_ddr_pre_training_fixup(void); int mv_ddr_post_training_fixup(void); int mv_ddr_manual_cal_do(void); int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size); + #endif /* _MV_DDR_PLAT_H */ |