ddr: marvell: a38x: add support for twin-die combined memory device

commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.

the twin-die combined memory device should be treatened as X8
device and not as X16 one

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
[ - the default value for twin_die_combined is set to NOT_COMBINED for
    all boards, as this was default behaviour prior this change ]
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

1 files changed, 12 insertions, 0 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 3991fec272..461f091472 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -14,6 +14,11 @@
 #define MV_DDR_MAX_BUS_NUM	9
 #define MV_DDR_MAX_IFACE_NUM	1
 
+enum mv_ddr_twin_die {
+	COMBINED,
+	NOT_COMBINED,
+};
+
 struct bus_params {
 	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
 	u8 cs_bitmask;
@@ -47,6 +52,9 @@ struct if_params {
 	/* The DDR frequency for each interfaces */
 	enum mv_ddr_freq memory_freq;
 
+    /* ddr twin-die */
+	enum mv_ddr_twin_die twin_die_combined;
+
 	/*
 	 * delay CAS Write Latency
 	 * - 0 for using default value (jedec suggested)
@@ -113,6 +121,9 @@ struct mv_ddr_topology_map {
 	/* source of ddr configuration data */
 	enum mv_ddr_cfg_src cfg_src;
 
+	/* ddr twin-die */
+	enum mv_ddr_twin_die twin_die_combined;
+
 	/* raw spd data */
 	union mv_ddr_spd_data spd_data;
 
@@ -193,6 +204,7 @@ struct mv_ddr_iface {
 
 	/* ddr interface topology map */
 	struct mv_ddr_topology_map tm;
+
 };
 
 struct mv_ddr_iface *mv_ddr_iface_get(void);