ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").

The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:

  ddr3: add missing txsdll parameter
  ddr3: fix tfaw timimg parameter
  ddr3: fix trrd timimg parameter
  merge ddr3 topology header file with mv_ddr_topology one
  mv_ddr: a38x: fix zero memory size scrubbing issue

The upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdef

    find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
        xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
                 -UCONFIG_APN806 -UCONFIG_MC_STATIC \
                 -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
                 -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
                 -UA70X0

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 5 insertions, 2 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_pbs.c b/drivers/ddr/marvell/a38x/ddr3_training_pbs.c
index 0511026afb..b7dfebd93c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_pbs.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_pbs.c
@@ -4,6 +4,9 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_training_db.h"
+#include "mv_ddr_common.h"
+#include "mv_ddr_regs.h"
 
 #define TYPICAL_PBS_VALUE	12
 
@@ -33,7 +36,7 @@ static u8 pup_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
 int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode)
 {
 	u32 res0[MAX_INTERFACE_NUM];
-	int adll_tap = MEGA / freq_val[medium_freq] / 64;
+	int adll_tap = MEGA / mv_ddr_freq_get(medium_freq) / 64;
 	int pad_num = 0;
 	enum hws_search_dir search_dir =
 		(pbs_mode == PBS_RX_MODE) ? HWS_HIGH2LOW : HWS_LOW2HIGH;
@@ -921,7 +924,7 @@ int ddr3_tip_pbs_tx(u32 uidev_num)
 int ddr3_tip_print_all_pbs_result(u32 dev_num)
 {
 	u32 curr_cs;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 
 	for (curr_cs = 0; curr_cs < max_cs; curr_cs++) {
 		ddr3_tip_print_pbs_result(dev_num, curr_cs, PBS_RX_MODE);