ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").

The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:

  ddr3: add missing txsdll parameter
  ddr3: fix tfaw timimg parameter
  ddr3: fix trrd timimg parameter
  merge ddr3 topology header file with mv_ddr_topology one
  mv_ddr: a38x: fix zero memory size scrubbing issue

The upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdef

    find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
        xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
                 -UCONFIG_APN806 -UCONFIG_MC_STATIC \
                 -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
                 -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
                 -UA70X0

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 5 insertions, 5 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
index f614d688c9..2df592e1b0 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
@@ -28,15 +28,15 @@ typedef int (*HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR)(
 	u8 dev_num, enum hws_access_type interface_access, u32 if_id,
 	u32 offset, u32 data, u32 mask);
 typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)(
-	u8 dev_num, enum hws_ddr_freq freq,
+	u8 dev_num, enum mv_ddr_freq freq,
 	struct hws_tip_freq_config_info *freq_config_info);
 typedef int (*HWS_TIP_GET_DEVICE_INFO)(
 	u8 dev_num, struct ddr3_device_info *info_ptr);
 typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)(
 	u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
 typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)(
-	u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
-typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq);
+	u8 dev_num, u32 if_id, enum mv_ddr_freq freq);
+typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum mv_ddr_freq *freq);
 typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)(
 	u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
 	u32 reg_addr, u32 data, u32 mask);
@@ -54,7 +54,7 @@ typedef int (*HWS_TRAINING_IP_ALGO_RUN_FUNC_PTR)(
 	u32 dev_num, enum hws_algo_type algo_type);
 typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)(
 	u32 dev_num, enum hws_access_type access_type, u32 if_id,
-	enum hws_ddr_freq frequency);
+	enum mv_ddr_freq frequency);
 typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)(
 	u32 dev_num, struct init_cntr_param *init_cntr_prm);
 typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num);
@@ -64,7 +64,7 @@ typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)(
 typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)(
 	u32 dev_num, struct mv_ddr_topology_map *tm);
 typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)(
-	u32 dev_num, enum hws_ddr_freq frequency,
+	u32 dev_num, enum mv_ddr_freq frequency,
 	enum hws_static_config_type static_config_type, u32 if_id);
 typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)(
 	u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);