ARM: mvebu: a38x: sync ddr training code with upstream

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef

  find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
    xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
		-UCONFIG_APN806 -UCONFIG_MC_STATIC \
		-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
		-UCONFIG_64BIT

INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.

Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 14 insertions, 3 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
index 352bc0ce26..f614d688c9 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
@@ -62,7 +62,7 @@ typedef int (*HWS_TRAINING_IP_PBS_TX_FUNC_PTR)(u32 dev_num);
 typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)(
 	u32 dev_num, int enable);
 typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)(
-	u32 dev_num, struct hws_topology_map *topology_map);
+	u32 dev_num, struct mv_ddr_topology_map *tm);
 typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)(
 	u32 dev_num, enum hws_ddr_freq frequency,
 	enum hws_static_config_type static_config_type, u32 if_id);
@@ -83,16 +83,27 @@ typedef int (*HWS_TRAINING_IP_LOAD_TOPOLOGY)(u32 dev_num, u32 config_num);
 typedef int (*HWS_TRAINING_IP_READ_LEVELING)(u32 dev_num, u32 config_num);
 typedef int (*HWS_TRAINING_IP_WRITE_LEVELING)(u32 dev_num, u32 config_num);
 typedef u32 (*HWS_TRAINING_IP_GET_TEMP)(u8 dev_num);
+typedef u8 (*HWS_TRAINING_IP_GET_RATIO)(u32 freq);
 
 struct hws_tip_config_func_db {
 	HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR tip_dunit_mux_select_func;
-	HWS_TIP_DUNIT_REG_READ_FUNC_PTR tip_dunit_read_func;
-	HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR tip_dunit_write_func;
+	void (*mv_ddr_dunit_read)(u32 addr, u32 mask, u32 *data);
+	void (*mv_ddr_dunit_write)(u32 addr, u32 mask, u32 data);
 	HWS_TIP_GET_FREQ_CONFIG_INFO tip_get_freq_config_info_func;
 	HWS_TIP_GET_DEVICE_INFO tip_get_device_info_func;
 	HWS_SET_FREQ_DIVIDER_FUNC_PTR tip_set_freq_divider_func;
 	HWS_GET_CS_CONFIG_FUNC_PTR tip_get_cs_config_info;
 	HWS_TRAINING_IP_GET_TEMP tip_get_temperature;
+	HWS_TRAINING_IP_GET_RATIO tip_get_clock_ratio;
+	HWS_TRAINING_IP_EXTERNAL_READ_PTR tip_external_read;
+	HWS_TRAINING_IP_EXTERNAL_WRITE_PTR tip_external_write;
+	int (*mv_ddr_phy_read)(enum hws_access_type phy_access,
+			       u32 phy, enum hws_ddr_phy phy_type,
+			       u32 reg_addr, u32 *data);
+	int (*mv_ddr_phy_write)(enum hws_access_type phy_access,
+				u32 phy, enum hws_ddr_phy phy_type,
+				u32 reg_addr, u32 data,
+				enum hws_operation op_type);
 };
 
 int ddr3_tip_init_config_func(u32 dev_num,