ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").

The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:

  ddr3: add missing txsdll parameter
  ddr3: fix tfaw timimg parameter
  ddr3: fix trrd timimg parameter
  merge ddr3 topology header file with mv_ddr_topology one
  mv_ddr: a38x: fix zero memory size scrubbing issue

The upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdef

    find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
        xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
                 -UCONFIG_APN806 -UCONFIG_MC_STATIC \
                 -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
                 -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
                 -UA70X0

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 0 insertions, 38 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
index 531103c1ab..056c21497c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
@@ -6,12 +6,8 @@
 #ifndef _DDR3_TRAINING_IP_H_
 #define _DDR3_TRAINING_IP_H_
 
-#include "ddr3_training_ip_def.h"
 #include "ddr_topology_def.h"
-#include "ddr_training_ip_db.h"
 
-#define MAX_CS_NUM		4
-#define MAX_TOTAL_BUS_NUM	(MAX_INTERFACE_NUM * MAX_BUS_NUM)
 #define TIP_ENG_LOCK	0x02000000
 #define TIP_TX_DLL_RANGE_MAX	64
 
@@ -112,40 +108,11 @@ struct pattern_info {
 	u8 pattern_len;
 };
 
-/* CL value for each frequency */
-struct cl_val_per_freq {
-	u8 cl_val[DDR_FREQ_LAST];
-};
-
 struct cs_element {
 	u8 cs_num;
 	u8 num_of_cs;
 };
 
-struct mode_info {
-	/* 32 bits representing MRS bits */
-	u32 reg_mr0[MAX_INTERFACE_NUM];
-	u32 reg_mr1[MAX_INTERFACE_NUM];
-	u32 reg_mr2[MAX_INTERFACE_NUM];
-	u32 reg_m_r3[MAX_INTERFACE_NUM];
-	/*
-	 * Each element in array represent read_data_sample register delay for
-	 * a specific interface.
-	 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR
-	 * cycles from read command until data is ready to be fetched from
-	 * the PHY, when accessing CS.
-	 */
-	u32 read_data_sample[MAX_INTERFACE_NUM];
-	/*
-	 * Each element in array represent read_data_sample register delay for
-	 * a specific interface.
-	 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay
-	 * from read command until opening the read mask, when accessing CS.
-	 * This field defines the delay in DDR cycles granularity.
-	 */
-	u32 read_data_ready[MAX_INTERFACE_NUM];
-};
-
 struct hws_tip_freq_config_info {
 	u8 is_supported;
 	u8 bw_per_freq;
@@ -173,12 +140,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num,
 int hws_ddr3_tip_load_topology_map(u32 dev_num,
 				   struct mv_ddr_topology_map *topology);
 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
-int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
-int hws_ddr3_tip_read_training_result(u32 dev_num,
-		enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
 u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
 u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
-uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void);
-uint64_t mv_ddr_get_total_memory_size_in_bits(void);
 #endif /* _DDR3_TRAINING_IP_H_ */