diff options
| author | Bo Gan <ganboing@gmail.com> | 2024-03-05 19:00:11 -0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-03-12 14:36:13 +0800 |
| commit | e6b7aeef3df206b9f2a47e715d643b735d18ae73 (patch) | |
| tree | 64208fb838045f841c787f24d5cb867c273d2310 /drivers/ddr/marvell/a38x/ddr3_training_bist.c | |
| parent | 0d95add3b1c7e17d979021505fcc138f74d95b88 (diff) | |
riscv: dts: jh7110: Enable PLL node in SPL
Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.
Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_bist.c')
0 files changed, 0 insertions, 0 deletions