diff options
| author | Chris Packham <judge.packham@gmail.com> | 2018-01-18 17:16:07 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2018-01-19 16:30:29 +0100 |
| commit | dbaf09590df9add19e738d2de03c0f2d0d8f5433 (patch) | |
| tree | 6d66ffa1424c606be07166f15469df243655251e /drivers/ddr/marvell/a38x/ddr3_init.h | |
| parent | 086ebcd40e9bf8efc520f1b177fd8e3cc0e506fa (diff) | |
ddr: marvell: only assert M_ODT[0] on write for a single CS
When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_init.h')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_init.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h index 8cb08864c2..a4c75a9fa6 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.h +++ b/drivers/ddr/marvell/a38x/ddr3_init.h @@ -183,7 +183,8 @@ extern u32 g_znodt_data; extern u32 g_zpodt_ctrl; extern u32 g_znodt_ctrl; extern u32 g_dic; -extern u32 g_odt_config; +extern u32 g_odt_config_2cs; +extern u32 g_odt_config_1cs; extern u32 g_rtt_nom; extern u8 debug_training_access; |