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authorYe Li <ye.li@nxp.com>2020-09-29 21:55:32 -0700
committerStefano Babic <sbabic@denx.de>2021-01-23 11:30:30 +0100
commit7c4f9b37556e8519216c4fd94913c9374d1ab610 (patch)
tree8aaf451caa443ce47a6857f74a909318db0e123e /drivers/ddr/imx/imx8m
parent846b77e7df4b0c24ed9f3bbc3c1d88aa03265f7c (diff)
imx: ddr: imx8m: Move selfref_en after DDR scrub
When doing DDR scrub, the DDR may enter into self refresh if the selfref_en is enabled before DDR scrub. This will cause scrub can't complete that SBRSTAT.scrub_done won't be set. Since the selfref_en can be programmed during the course of normal operation, move it after DDR scrub Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr/imx/imx8m')
-rw-r--r--drivers/ddr/imx/imx8m/ddr_init.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index 99a67edfb0..b70bcc383f 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -235,8 +235,6 @@ int ddr_init(struct dram_timing_info *dram_timing)
/* Step26: Set back register in Step4 to the original values if desired */
reg32_write(DDRC_RFSHCTL3(0), 0x0000000);
- /* enable selfref_en by default */
- setbits_le32(DDRC_PWRCTL(0), 0x1);
/* enable port 0 */
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
@@ -244,6 +242,9 @@ int ddr_init(struct dram_timing_info *dram_timing)
board_dram_ecc_scrub();
+ /* enable selfref_en by default */
+ setbits_le32(DDRC_PWRCTL(0), 0x1);
+
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);