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| author | Michal Simek <michal.simek@xilinx.com> | 2020-10-23 04:59:00 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-10-27 08:13:33 +0100 |
| commit | 80355ae40dfceb2304ed287846a3d3292e65d323 (patch) | |
| tree | 137530410f821bbc7fb23af9a57ef872a1c9455d /drivers/ddr/fsl | |
| parent | 9851f50d3d8e8a933a072b11f7f497846b068fb8 (diff) | |
mmc: zynq_sdhci: Read clock phase delays from dt
Define input and output clock phase delays with pre-defined values.
Define arasan_sdhci_clk_data type structure and add it to priv
structure and store these clock phase delays in it.
Read input and output clock phase delays from dt. If these values are
not passed through dt, use pre-defined values.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'drivers/ddr/fsl')
0 files changed, 0 insertions, 0 deletions