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| author | Dario Binacchi <dariobin@libero.it> | 2021-06-02 22:38:01 +0200 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2021-06-09 22:23:44 +0530 |
| commit | 79250ef3e263ef23c16c3c06a50834f0dcca4426 (patch) | |
| tree | 99fd0aa16b754472f247bb4b83132d784b12c6e2 /drivers/ddr/fsl | |
| parent | 82a456a085facede0913a742660df9a1607d1543 (diff) | |
rtc: davinci: check BUSY bit before set TC registers
To write correct data to the TC registers, the STATUS register must be
read until the BUSY bit is equal to zero. Once the BUSY flag is zero,
there is a 15 μs access period in which the TC registers can be
programmed.
The rtc_wait_not_busy() has been inspired by the Kernel.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210602203805.11494-5-dariobin@libero.it
Diffstat (limited to 'drivers/ddr/fsl')
0 files changed, 0 insertions, 0 deletions