diff options
author | Tom Rini <trini@konsulko.com> | 2023-01-20 14:21:38 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-01-20 14:21:38 -0500 |
commit | 0b9b01517f0b1398ec27dbb47faf3645b719e02c (patch) | |
tree | fac11441ba4056e75d3b59811da3b0a91d1cfcf5 /drivers/ddr/fsl/ctrl_regs.c | |
parent | 8bd3c0a7e17ee17c771cabc0e548a1a436ac021d (diff) | |
parent | 6333acb961b6fcaa60c6e5b623d676b332481cfa (diff) |
Merge branch '2023-01-20-finish-CONFIG-migration-work'
- Merge in the final batch of CONFIG to Kconfig/CFG migration work. This
includes a fix for a number of ns16550 or similar UARTs due to a
migration bug. We also pull in a revert for enabling CONFIG_VIDEO on
tools-only_defconfig.
Diffstat (limited to 'drivers/ddr/fsl/ctrl_regs.c')
-rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 759921bc58..8f8c2c864c 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -822,7 +822,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, twot_en = popts->twot_en; } - sdram_type = CONFIG_FSL_SDRAM_TYPE; + sdram_type = CFG_FSL_SDRAM_TYPE; dyn_pwr = popts->dynamic_power; dbw = popts->data_bus_width; @@ -926,7 +926,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, rcw_en = 1; /* DDR4 can have address parity for UDIMM and discrete */ - if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) && + if ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) && (!popts->registered_dimm_en)) { ap_en = 0; } else { @@ -1188,7 +1188,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, * handled by register chip and RCW settings. */ if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && - ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) || + ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) || !popts->registered_dimm_en)) { if (mclk_ps >= 935) { /* for DDR4-1600/1866/2133 */ @@ -1223,7 +1223,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, } if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && - ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) || + ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) || !popts->registered_dimm_en)) { if (mclk_ps >= 935) { /* for DDR4-1600/1866/2133 */ @@ -1983,7 +1983,7 @@ static void set_timing_cfg_7(const unsigned int ctrl_num, tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN && - CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) { + CFG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) { /* for DDR4 only */ par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1; debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps); |