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| author | Tudor Ambarus <tudor.ambarus@microchip.com> | 2021-11-03 18:47:10 +0200 |
|---|---|---|
| committer | Eugen Hristev <eugen.hristev@microchip.com> | 2021-12-07 08:55:22 +0200 |
| commit | 2fd1b97f33c91e9878d24a0f251ba0d2104e9e71 (patch) | |
| tree | 7dde154edcf6ae53d9f856dae6a2fa065bb3b28e /drivers/ddr/fsl/arm_ddr_gen3.c | |
| parent | 7dc48b41f4f3e00d9865308605cb3831d7a6c1fb (diff) | |
spi: atmel-quadspi: Add support for SAMA7G5 QSPI
sama7g5 QSPI has:
1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to
200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported
2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to
90 MHz DDR/133 MHz SDR
The QSPI controller of SAMA7G5 uses different clock domains, hence extra
synchronization operations must be performed before accessing some
registers. Differentiate between the versions of the IP using has_gclk.
Differentiate between QSPI0 and QSPI1 with has_octal.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/ddr/fsl/arm_ddr_gen3.c')
0 files changed, 0 insertions, 0 deletions