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| author | Tom Rini <trini@konsulko.com> | 2020-07-17 16:08:54 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-17 16:08:54 -0400 |
| commit | 1c4b5038afcc7cdb1064713f65571da05aa0de0e (patch) | |
| tree | bbb554b1128dc15453a91fc50408446da2e0ddd2 /drivers/ddr/altera/sdram_s10.c | |
| parent | 7c3cc6f106ed1ca13b0ff6eea9f8e1473240aef3 (diff) | |
| parent | 21fc5a16855602b2fd4b39e40679f854101a0fa3 (diff) | |
Merge branch '2020-07-17-misc-fixes'
A large number of assorted fixes, including but not limited to:
- Correct fixdep and CONFIG_IS_ENABLED(...)
- lz4 on big endian
- Assorted LMB hardening
- Remove bd_t typedef
Diffstat (limited to 'drivers/ddr/altera/sdram_s10.c')
| -rw-r--r-- | drivers/ddr/altera/sdram_s10.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 91f76e03c2..2945f1e1df 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -76,7 +76,7 @@ int sdram_mmr_init_full(struct udevice *dev) u32 i; int ret; phys_size_t hw_size; - bd_t bd = {0}; + struct bd_info bd = {0}; /* Enable access to DDR from CPU master */ clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG), |