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| author | Tom Rini <trini@konsulko.com> | 2022-09-18 08:34:31 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-09-18 08:34:31 -0400 |
| commit | b6c50e5831f6ce3800d4b3cf3c7aa35dde8c48d9 (patch) | |
| tree | 4403d1b2ff259014c01855e08191ad0d1c294741 /drivers/ddr/altera/sdram_n5x.c | |
| parent | d219fc06b30d4b1ac4fac6c40b2ca69cb5ecf642 (diff) | |
| parent | 8695fbb3a7ff3640eff62f7123323b16546d5b35 (diff) | |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-watchdog into next
- Migrate watchdog reset to cyclic infrastructure (Stefan)
Diffstat (limited to 'drivers/ddr/altera/sdram_n5x.c')
| -rw-r--r-- | drivers/ddr/altera/sdram_n5x.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 737a4e2ff1..d9039443b9 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -517,7 +517,7 @@ static int ensure_retry_procedure_complete(phys_addr_t umctl2_base) DDR4_CRCPARSTAT_CMD_IN_ERR_WINDOW; udelay(1); - WATCHDOG_RESET(); + schedule(); } return 0; @@ -1349,7 +1349,7 @@ static int ddr_post_handoff_config(phys_addr_t umctl2_base, } udelay(1); - WATCHDOG_RESET(); + schedule(); /* Polling until SDRAM entered normal operating mode */ value = readl(umctl2_base + DDR4_STAT_OFFSET) & |