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authorJerome Brunet <jbrunet@baylibre.com>2020-03-05 12:12:37 +0100
committerNeil Armstrong <narmstrong@baylibre.com>2020-04-06 09:56:35 +0200
commitb3d69aa596599c7c940f7ad463c04b693589ff9a (patch)
tree5f484ddaee3f851539019d5d1a683457626cfc45 /drivers/clk/meson/g12a.c
parent0392416fb1f2d8ff91ca6ec0471fc891445406e5 (diff)
clk: meson: reset mmc clock on probe
On some SoCs, depending on the boot device, the MMC clock block may be left in a weird state by the ROM code, in which no decent clock may be provided. Reset the related register to make sure a sane MMC clock is ready for the controller. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/g12a.c')
-rw-r--r--drivers/clk/meson/g12a.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index cada80e6b5..c1976aa1ef 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -978,6 +978,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+ * Depending on the boot src, the state of the MMC clock might
+ * be different. Reset it to make sure we won't get stuck
+ */
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk-g12a: probed\n");
return 0;