diff options
| author | Tom Rini <trini@konsulko.com> | 2023-07-21 09:57:59 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-07-21 09:57:59 -0400 |
| commit | e7f7e2e1e22fd719a8810ba488a9451635b13d1b (patch) | |
| tree | 0dda2ed98b772b44ae61b041d402f9618cd18670 /drivers/clk/clk_zynqmp.c | |
| parent | e896279ac39ebb97f23e6132bf7668a61e1cd86b (diff) | |
| parent | a1190b4d6a9bf3a45038e3eba4a11de4be2b1cca (diff) | |
Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.10-rc1 v2
axi_emac:
- Change return value if RX packet is not ready
cadence_qspi:
- Enable flash reset for Versal NET
dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location
fpga:
- Add load event
mtd:
- Add missing dependency for FLASH_CFI_MTD
spi/nand:
- Minor cleanup in Xilinx drivers
versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations
watchdog:
- Use new versal-wwdt property
xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email
zynqmp_clk:
- Add handling for gem rx/tsu clocks
zynq_gem:
- Configure mdio clock at run time
zynq:
- Enable fdt overlay support
zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
Diffstat (limited to 'drivers/clk/clk_zynqmp.c')
| -rw-r--r-- | drivers/clk/clk_zynqmp.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index be0ee50e0e..1cfe0e25b1 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -12,6 +12,7 @@ #include <linux/bitops.h> #include <clk-uclass.h> #include <clk.h> +#include <zynqmp_firmware.h> #include <asm/arch/sys_proto.h> #include <dm.h> #include <linux/err.h> @@ -269,17 +270,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) case usb3_dual_ref: return CRL_APB_USB3_DUAL_REF_CTRL; case gem_tsu_ref: + case gem_tsu: return CRL_APB_GEM_TSU_REF_CTRL; case gem0_tx: + case gem0_rx: case gem0_ref: return CRL_APB_GEM0_REF_CTRL; case gem1_tx: + case gem1_rx: case gem1_ref: return CRL_APB_GEM1_REF_CTRL; case gem2_tx: + case gem2_rx: case gem2_ref: return CRL_APB_GEM2_REF_CTRL; case gem3_tx: + case gem3_rx: case gem3_ref: return CRL_APB_GEM3_REF_CTRL; case usb0_bus_ref: @@ -718,6 +724,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) switch (id) { case gem0_ref ... gem3_ref: case gem0_tx ... gem3_tx: + case gem0_rx ... gem3_rx: + case gem_tsu: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: return zynqmp_clk_set_peripheral_rate(priv, id, |