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| author | Tom Rini <trini@konsulko.com> | 2021-02-23 10:45:55 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-02-23 10:45:55 -0500 |
| commit | cbe607b920bc0827d8fe379ed4f5ae4e2058513e (patch) | |
| tree | b8cdbb8856766675f37bb92f27ab9c662fa647f9 /drivers/clk/clk_versal.c | |
| parent | 8f7a16aac36c2a38956bd04b53cb7b94b7a70180 (diff) | |
| parent | d9aa19efa8a6c20d51b7884de0a7f8dae3f835d2 (diff) | |
Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.04-rc3
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
Diffstat (limited to 'drivers/clk/clk_versal.c')
| -rw-r--r-- | drivers/clk/clk_versal.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 908bc7519c..62523d2909 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -718,9 +718,20 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate) return clk_rate; } +static int versal_clk_enable(struct clk *clk) +{ + struct versal_clk_priv *priv = dev_get_priv(clk->dev); + u32 clk_id; + + clk_id = priv->clk[clk->id].clk_id; + + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); +} + static struct clk_ops versal_clk_ops = { .set_rate = versal_clk_set_rate, .get_rate = versal_clk_get_rate, + .enable = versal_clk_enable, }; static const struct udevice_id versal_clk_ids[] = { |