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authorClaudiu Beznea <claudiu.beznea@microchip.com>2023-03-08 16:39:52 +0200
committerEugen Hristev <eugen.hristev@collabora.com>2023-03-27 14:27:37 +0300
commit248e41002b0424f098d8776718b80669a3759e87 (patch)
treef803bcce6db4e828e5939a097033f22a88aff53b /drivers/clk/at91/pmc.c
parentc88a925a3a58356869199381288e7ecc11a87b26 (diff)
clk: at91: pmc: export clock setup to pmc
Clock setup was intended for setting clocks at boot time on SAMA7G5, e.g. for root clocks like PLLs, that were used to feed IPs needed alive in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality to all at91 clocks as it may be necessary on other SoCs. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Diffstat (limited to 'drivers/clk/at91/pmc.c')
-rw-r--r--drivers/clk/at91/pmc.c42
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 270892517a..87d2069d89 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -120,3 +120,45 @@ int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index)
return table[index];
}
+
+int at91_clk_setup(const struct pmc_clk_setup *setup, int size)
+{
+ struct clk *c, *parent;
+ int i, ret;
+
+ if (!size)
+ return 0;
+
+ if (!setup)
+ return -EINVAL;
+
+ for (i = 0; i < size; i++) {
+ ret = clk_get_by_id(setup[i].cid, &c);
+ if (ret)
+ return ret;
+
+ if (setup[i].pid) {
+ ret = clk_get_by_id(setup[i].pid, &parent);
+ if (ret)
+ return ret;
+
+ ret = clk_set_parent(c, parent);
+ if (ret)
+ return ret;
+
+ if (setup[i].prate) {
+ ret = clk_set_rate(parent, setup[i].prate);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ if (setup[i].rate) {
+ ret = clk_set_rate(c, setup[i].rate);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ return 0;
+}