diff options
| author | Tom Rini <trini@ti.com> | 2013-03-11 12:02:40 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 12:16:13 -0400 |
| commit | 76b40ab41eff1f402ee52ba768b09daad293b9bb (patch) | |
| tree | 4956296adbdc8939aa49d84fa9bd497eef65b7f4 /common/cmd_reginfo.c | |
| parent | de62688bb61c499ecc2d70a3aa8ccf90bb7a8ef6 (diff) | |
| parent | fc959081d41aab2d6f4614c5fb3dd1b77ffcdcf4 (diff) | |
Merge u-boot/master into u-boot-ti/master
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these
conflicts manually and comment the #else/#endif lines for clarity.
Conflicts:
arch/arm/include/asm/arch-davinci/gpio.h
drivers/gpio/da8xx_gpio.c
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'common/cmd_reginfo.c')
| -rw-r--r-- | common/cmd_reginfo.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 08a6563448..b591bd3774 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -191,7 +191,7 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, #elif defined(CONFIG_BLACKFIN) puts("\nSystem Configuration registers\n"); - +#ifndef __ADSPBF60x__ puts("\nPLL Registers\n"); printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n", bfin_read_PLL_DIV(), bfin_read_PLL_CTL()); @@ -227,7 +227,24 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); # endif +#else + puts("\nCGU Registers\n"); + printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n", + bfin_read_CGU_DIV(), bfin_read_CGU_CTL()); + printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n", + bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL()); + puts("\nSMC DDR Registers\n"); + printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n", + bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0()); + printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n", + bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2()); + printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n", + bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1()); + printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n", + bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT()); + printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL()); +#endif #endif /* CONFIG_BLACKFIN */ return 0; |