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| author | Stefan Mätje <stefan.maetje@esd.eu> | 2021-11-30 01:06:56 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-01-16 08:31:03 -0500 |
| commit | a6e562fe36b2bae780589a81a11fceb6e1b4a9f7 (patch) | |
| tree | ec452c000cdc36d7e3fcf0acc3b0e998e9e5b2d2 /common/board_r.c | |
| parent | 5ce7df1078a506f01d63d821b6531fac86e079b9 (diff) | |
Fix wrong QSPI clock calculation for AM4372
On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.
The QSPI_FCLK therefore needs to take this factor into account and
becomes (192000000 / 4).
Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
Diffstat (limited to 'common/board_r.c')
0 files changed, 0 insertions, 0 deletions