Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.10-rc1 v2

axi_emac:
- Change return value if RX packet is not ready

cadence_qspi:
- Enable flash reset for Versal NET

dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location

fpga:
- Add load event

mtd:
- Add missing dependency for FLASH_CFI_MTD

spi/nand:
- Minor cleanup in Xilinx drivers

versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations

watchdog:
- Use new versal-wwdt property

xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email

zynqmp_clk:
- Add handling for gem rx/tsu clocks

zynq_gem:
- Configure mdio clock at run time

zynq:
- Enable fdt overlay support

zynq_sdhci:
- Call dll reset only for ZynqMP SOCs

1 files changed, 2 insertions, 2 deletions

diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index c2a6f9199a..602a789e77 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -12408,7 +12408,7 @@ unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
 unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
 
 int
-ps7_post_config()
+ps7_post_config(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();
@@ -12427,7 +12427,7 @@ ps7_post_config()
 }
 
 int
-ps7_init()
+ps7_init(void)
 {
   // Get the PS_VERSION on run time
   unsigned long si_ver = ps7GetSiliconVersion ();