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| author | Tom Rini <trini@konsulko.com> | 2023-06-09 10:30:26 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-06-09 10:30:26 -0400 |
| commit | ac7ca692092a100e97a79531d2f707f1ca7faaaa (patch) | |
| tree | d5cb497991cdf09e1ebd3407f1b367050c71e1e8 /board/renesas/rcar-common | |
| parent | 3aa4fb12f4abd31bce7fe6294dd47fd0966a791a (diff) | |
| parent | ed2f65f0105dacb98e5c4d2b435dd009de06c2d1 (diff) | |
Merge branch 'next_soc/v3x' of https://source.denx.de/u-boot/custodians/u-boot-sh into next
Diffstat (limited to 'board/renesas/rcar-common')
| -rw-r--r-- | board/renesas/rcar-common/common.c | 42 | ||||
| -rw-r--r-- | board/renesas/rcar-common/v3-common.c | 41 |
2 files changed, 83 insertions, 0 deletions
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index f38453af82..3a0e88b391 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -10,8 +10,10 @@ #include <common.h> #include <dm.h> #include <fdt_support.h> +#include <hang.h> #include <init.h> #include <asm/global_data.h> +#include <asm/io.h> #include <dm/uclass-internal.h> #include <asm/arch/rmobile.h> #include <linux/libfdt.h> @@ -47,6 +49,46 @@ int dram_init_banksize(void) return 0; } +int __weak board_init(void) +{ + return 0; +} + +#if defined(CONFIG_RCAR_GEN3) +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void __weak reset_cpu(void) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} +#elif defined(CONFIG_RCAR_GEN4) +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 + +void __weak reset_cpu(void) +{ + writel(RST_SPRES, RST_SRESCR0); +} +#else +#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set +#endif + #if defined(CONFIG_OF_BOARD_SETUP) static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node) { diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/rcar-common/v3-common.c new file mode 100644 index 0000000000..7c6202ea49 --- /dev/null +++ b/board/renesas/rcar-common/v3-common.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org> + */ + +#include <common.h> +#include <clock_legacy.h> +#include <asm/io.h> + +#define CPGWPR 0xE6150900 +#define CPGWPCR 0xE6150904 + +/* PLL */ +#define PLL0CR 0xE61500D8 +#define PLL0_STC_MASK 0x7F000000 +#define PLL0_STC_OFFSET 24 + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 0.8GHz */ + stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); +} + +int board_early_init_f(void) +{ + /* Unlock CPG access */ + writel(0xA5A5FFFF, CPGWPR); + writel(0x5A5A0000, CPGWPCR); + + return 0; +} |