diff options
| author | Tom Rini <trini@konsulko.com> | 2022-09-23 18:42:53 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-09-23 18:42:53 -0400 |
| commit | 694e9008674c2008b9ccdc25a9bb3ac078e20911 (patch) | |
| tree | 8ab2a2636dc86ebb2ccb312512d5f402cf2b3e7e /board/imgtec/boston/ddr.c | |
| parent | 4057d64fae78e1e9bf8a5a87a823f188a1339917 (diff) | |
| parent | 236f73962718511e801f4ec9562075e86f737ec4 (diff) | |
Merge branch '2022-09-23-4gb-ddr-in-32bit-ppc' into next
To quote the author, for the first 9 patches:
This patch series fixes U-Boot code to correctly handle RAM size larger
than 2 GB and then fixes fsl ddr driver to do not crash U-Boot when 4 GB
DDR module is detected when U-Boot operates in 32-bit mode (as opposite
of the 36-bit mode).
With this patch series it is possible to boot 32-bit U-Boot with 4 GB
SODIMM DDR3 module without crashes. U-Boot will still use just
CONFIG_MAX_MEM_MAPPED amount of RAM, but it is better than crashing due
to the truncating of 4GB value to 32-bit number (which is zero).
I tested this patch series on powerpc P2020 based board but only with
U-Boot v2022.04 because U-Boot master branch is still broken on P2020.
And then the final two patches here are (in my mind at least) related
clean-ups.
Diffstat (limited to 'board/imgtec/boston/ddr.c')
| -rw-r--r-- | board/imgtec/boston/ddr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c index 182f79b918..5b245cb447 100644 --- a/board/imgtec/boston/ddr.c +++ b/board/imgtec/boston/ddr.c @@ -23,7 +23,7 @@ int dram_init(void) return 0; } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { DECLARE_GLOBAL_DATA_PTR; |