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| author | Ye Li <ye.li@nxp.com> | 2021-08-07 16:01:11 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-08-09 14:46:51 +0200 |
| commit | 7a6577fed4948a8540f1231ce1e6e7c96816d005 (patch) | |
| tree | e07ed5a7e92ccf303a814390557360bcc1fc926e /board/freescale/imx8ulp_evk/ddr_init.c | |
| parent | 3e2379418122555779e771e9289e744476974f9c (diff) | |
ddr: Add DDR driver for iMX8ULP
Add iMX8ULP DDR initialization driver which loads the DDR timing
parameters and executes the training procedure.
When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode
to do DDR init
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'board/freescale/imx8ulp_evk/ddr_init.c')
0 files changed, 0 insertions, 0 deletions