Merge branch 'for-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx

- A fix for a long standing bug that has been exposed by commit
  50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards
  from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.

1 files changed, 65 insertions, 0 deletions

diff --git a/board/cssi/mcr3000/nand.c b/board/cssi/mcr3000/nand.c
new file mode 100644
index 0000000000..11aca4ff73
--- /dev/null
+++ b/board/cssi/mcr3000/nand.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ */
+
+#include <config.h>
+#include <common.h>
+#include <nand.h>
+#include <linux/mtd/rawnand.h>
+#include <asm/io.h>
+
+#define BIT_CLE			((unsigned short)0x0800)
+#define BIT_ALE			((unsigned short)0x0400)
+#define BIT_NCE			((unsigned short)0x1000)
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this	= mtd_to_nand(mtdinfo);
+	immap_t __iomem *immr	= (immap_t __iomem *)CONFIG_SYS_IMMR;
+	unsigned short pddat	= 0;
+
+	/* The hardware control change */
+	if (ctrl & NAND_CTRL_CHANGE) {
+		pddat = in_be16(&immr->im_ioport.iop_pddat);
+
+		/* Clearing ALE and CLE */
+		pddat &= ~(BIT_CLE | BIT_ALE);
+
+		/* Driving NCE pin */
+		if (ctrl & NAND_NCE)
+			pddat &= ~BIT_NCE;
+		else
+			pddat |= BIT_NCE;
+
+		/* Driving CLE and ALE pin */
+		if (ctrl & NAND_CLE)
+			pddat |= BIT_CLE;
+		if (ctrl & NAND_ALE)
+			pddat |= BIT_ALE;
+
+		out_be16(&immr->im_ioport.iop_pddat, pddat);
+	}
+
+	/* Writing the command */
+	if (cmd != NAND_CMD_NONE)
+		out_8(this->IO_ADDR_W, cmd);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	immap_t __iomem *immr	= (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/* Set GPIO Port */
+	setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
+	clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
+	clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
+
+	nand->chip_delay	= 60;
+	nand->ecc.mode		= NAND_ECC_SOFT;
+	nand->cmd_ctrl		= nand_hwcontrol;
+
+	return 0;
+}