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| author | Tom Rini <trini@konsulko.com> | 2023-08-21 17:32:17 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-08-21 17:32:17 -0400 |
| commit | 7e6e40c572332b3835c5cb48a08e1d8d404c871c (patch) | |
| tree | cf8ebf03fbe72c1334880f75fe2c9f71c7bb95ff /board/asus/grouper/grouper-spl-ti.c | |
| parent | 3881c9fbb7fdd98f6eae5cd33f7e9abe9455a585 (diff) | |
| parent | 976fb2ffa3875a7bed9866bf5cf939a81c423ef8 (diff) | |
Merge tag 'v2023.10-rc3' into next
Prepare v2023.10-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/asus/grouper/grouper-spl-ti.c')
| -rw-r--r-- | board/asus/grouper/grouper-spl-ti.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/board/asus/grouper/grouper-spl-ti.c b/board/asus/grouper/grouper-spl-ti.c new file mode 100644 index 0000000000..e5b78f0121 --- /dev/null +++ b/board/asus/grouper/grouper-spl-ti.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 Grouper TI SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} |