diff options
| author | Tom Rini <trini@konsulko.com> | 2023-03-16 12:17:48 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-03-16 12:17:48 -0400 |
| commit | e63828bf35ac5632bd584980df5014c7c3e8c44d (patch) | |
| tree | 6a783c23031c7c76cef8353dc5199348ace46190 /arch | |
| parent | f6546c78221f2ed139ec6ad3a32285d4ef96a6ce (diff) | |
| parent | b07a62c0219ede896a20e825ab0791fb01d68407 (diff) | |
Merge tag 'fsl-qoriq-next-2023-3-14' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
Enable DM_SERIAL for freescale ls2080a
Drop non DM_ETH code for freescale:
lx2160a/ls2080rdb/ls2080aqds/ls1088a
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/fsl-ls1088a-rdb.dts | 4 | ||||
| -rw-r--r-- | arch/arm/dts/fsl-ls2080a.dtsi | 57 |
2 files changed, 46 insertions, 15 deletions
diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index ad059437b5..01f8fcb61a 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -19,13 +19,13 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xgmii"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; phy-handle = <&mdio2_phy1>; - phy-connection-type = "xgmii"; + phy-connection-type = "10gbase-r"; }; &dpmac3 { diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index a1837454f4..d754eb4d5c 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -6,18 +6,32 @@ * Copyright 2013-2015 Freescale Semiconductor, Inc. */ +#include <dt-bindings/clock/fsl,qoriq-clockgen.h> + / { compatible = "fsl,ls2080a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x80000000>; /* DRAM space - 1, size : 2 GB DRAM */ }; + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ @@ -35,20 +49,37 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; - serial0: serial@21c0500 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ - }; + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + + clockgen: clocking@1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; - serial1: serial@21c0600 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + serial0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + interrupts = <0 32 0x4>; /* Level high type */ + bootph-all; + }; + + serial1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + interrupts = <0 32 0x4>; /* Level high type */ + bootph-all; + }; }; i2c0: i2c@2000000 { |