Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- Provide serial base clock speed via getinfo() for ACPI SPCR
- Initial ACPI support from DM core by leveraging existing ACPI support
  in x86

26 files changed, 103 insertions, 425 deletions

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 4a277934a7..5fa951ad4b 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -206,6 +206,10 @@
 		compatible = "denx,u-boot-devres-test";
 	};
 
+	acpi-test {
+		compatible = "denx,u-boot-acpi-test";
+	};
+
 	clocks {
 		clk_fixed: clk-fixed {
 			compatible = "fixed-clock";
diff --git a/arch/sandbox/include/asm/acpi_table.h b/arch/sandbox/include/asm/acpi_table.h
new file mode 100644
index 0000000000..921c7f4201
--- /dev/null
+++ b/arch/sandbox/include/asm/acpi_table.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c
index 8a39c3128e..e2509e391f 100644
--- a/arch/x86/cpu/apollolake/cpu_spl.c
+++ b/arch/x86/cpu/apollolake/cpu_spl.c
@@ -6,13 +6,13 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <dm.h>
 #include <ec_commands.h>
 #include <log.h>
 #include <spi_flash.h>
 #include <spl.h>
 #include <syscon.h>
+#include <acpi/acpi_s3.h>
 #include <asm/cpu.h>
 #include <asm/cpu_common.h>
 #include <asm/cpu_x86.h>
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 1f22c1ea3c..17cf1682ad 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -5,11 +5,11 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <binman.h>
 #include <dm.h>
 #include <irq.h>
 #include <malloc.h>
+#include <acpi/acpi_s3.h>
 #include <asm/intel_pinctrl.h>
 #include <asm/io.h>
 #include <asm/intel_regs.h>
diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c
index aec0c8394c..4ea7c7447b 100644
--- a/arch/x86/cpu/apollolake/pmc.c
+++ b/arch/x86/cpu/apollolake/pmc.c
@@ -9,10 +9,10 @@
 #define LOG_CATEGORY UCLASS_ACPI_PMC
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <dt-structs.h>
 #include <dm.h>
 #include <spl.h>
+#include <acpi/acpi_s3.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <power/acpi_pmc.h>
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index f44228e693..5772310979 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -4,15 +4,15 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <cpu.h>
 #include <dm.h>
-#include <dm/uclass-internal.h>
-#include <asm/acpi_table.h>
+#include <acpi/acpi_s3.h>
+#include <acpi/acpi_table.h>
 #include <asm/io.h>
 #include <asm/tables.h>
 #include <asm/arch/global_nvs.h>
 #include <asm/arch/iomap.h>
+#include <dm/uclass-internal.h>
 
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 		      void *dsdt)
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index e698200d70..e8ccaf2212 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * This file is part of the coreboot project.
- *
  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * Modified from the coreboot version
  */
 
 #include <common.h>
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index dae06949cc..cec04b481b 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -19,7 +19,6 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <command.h>
 #include <cpu_func.h>
 #include <dm.h>
@@ -27,8 +26,9 @@
 #include <init.h>
 #include <malloc.h>
 #include <syscon.h>
+#include <acpi/acpi_s3.h>
+#include <acpi/acpi_table.h>
 #include <asm/acpi.h>
-#include <asm/acpi_table.h>
 #include <asm/control_regs.h>
 #include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
index d5b4846e0a..6f3c441618 100644
--- a/arch/x86/cpu/intel_common/p2sb.c
+++ b/arch/x86/cpu/intel_common/p2sb.c
@@ -92,46 +92,35 @@ int p2sb_ofdata_to_platdata(struct udevice *dev)
 
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	int ret;
+	u32 base[2];
 
+	ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
+	if (ret)
+		return log_msg_ret("Missing/short early-regs", ret);
+	plat->mmio_base = base[0];
+	/* TPL sets up the initial BAR */
 	if (spl_phase() == PHASE_TPL) {
-		u32 base[2];
-
-		/* TPL sets up the initial BAR */
-		ret = dev_read_u32_array(dev, "early-regs", base,
-					 ARRAY_SIZE(base));
-		if (ret)
-			return log_msg_ret("Missing/short early-regs", ret);
-		plat->mmio_base = base[0];
 		plat->bdf = pci_get_devfn(dev);
 		if (plat->bdf < 0)
 			return log_msg_ret("Cannot get p2sb PCI address",
 					   plat->bdf);
 	}
+	upriv->mmio_base = plat->mmio_base;
 #else
 	plat->mmio_base = plat->dtplat.early_regs[0];
 	plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
-#endif
 	upriv->mmio_base = plat->mmio_base;
-	debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base);
+#endif
 
 	return 0;
 }
 
 static int p2sb_probe(struct udevice *dev)
 {
-	if (spl_phase() == PHASE_TPL) {
+	if (spl_phase() == PHASE_TPL)
 		return p2sb_early_init(dev);
-	} else {
-		struct p2sb_platdata *plat = dev_get_platdata(dev);
-
-		plat->mmio_base = dev_read_addr_pci(dev);
-		/* Don't set BDF since it should not be used */
-		if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE)
-			return -EINVAL;
-
-		if (spl_phase() == PHASE_SPL)
-			return p2sb_spl_init(dev);
-	}
+	else if (spl_phase() == PHASE_SPL)
+		return p2sb_spl_init(dev);
 
 	return 0;
 }
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
index 7b6fc2f4a5..26cda3b337 100644
--- a/arch/x86/cpu/quark/acpi.c
+++ b/arch/x86/cpu/quark/acpi.c
@@ -4,7 +4,7 @@
  */
 
 #include <common.h>
-#include <asm/acpi_table.h>
+#include <acpi/acpi_table.h>
 #include <asm/tables.h>
 #include <asm/arch/global_nvs.h>
 #include <asm/arch/iomap.h>
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index 8b128138b0..4ec8fdd6f8 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -8,13 +8,13 @@
 #include <common.h>
 #include <cpu.h>
 #include <dm.h>
-#include <dm/uclass-internal.h>
-#include <asm/acpi_table.h>
+#include <acpi/acpi_table.h>
 #include <asm/ioapic.h>
 #include <asm/mpspec.h>
 #include <asm/tables.h>
 #include <asm/arch/global_nvs.h>
 #include <asm/arch/iomap.h>
+#include <dm/uclass-internal.h>
 
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 		      void *dsdt)
diff --git a/arch/x86/cpu/wakeup.S b/arch/x86/cpu/wakeup.S
index 244ca1276a..093bf3bcc5 100644
--- a/arch/x86/cpu/wakeup.S
+++ b/arch/x86/cpu/wakeup.S
@@ -5,7 +5,7 @@
  * From coreboot src/arch/x86/wakeup.S
  */
 
-#include <acpi_s3.h>
+#include <acpi/acpi_s3.h>
 #include <asm/processor.h>
 #include <asm/processor-flags.h>
 
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index af52e11c89..d48ef3573e 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -292,7 +292,7 @@
 				reg = <0x50>;
 				compatible = "google,cr50";
 				u-boot,i2c-offset-len = <0>;
-				ready-gpio = <&gpio_n 28 GPIO_ACTIVE_LOW>;
+				ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
 				interrupts-extended = <&acpi_gpe 0x3c 0>;
 			};
 		};
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 7588913f93..928475cef4 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -9,381 +9,14 @@
 #ifndef __ASM_ACPI_TABLE_H__
 #define __ASM_ACPI_TABLE_H__
 
-#define RSDP_SIG		"RSD PTR "	/* RSDP pointer signature */
-#define OEM_ID			"U-BOOT"	/* U-Boot */
-#define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */
-#define ASLC_ID			"INTL"		/* Intel ASL Compiler */
-
-#define ACPI_RSDP_REV_ACPI_1_0	0
-#define ACPI_RSDP_REV_ACPI_2_0	2
-
-/*
- * RSDP (Root System Description Pointer)
- * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
- */
-struct acpi_rsdp {
-	char signature[8];	/* RSDP signature */
-	u8 checksum;		/* Checksum of the first 20 bytes */
-	char oem_id[6];		/* OEM ID */
-	u8 revision;		/* 0 for ACPI 1.0, others 2 */
-	u32 rsdt_address;	/* Physical address of RSDT (32 bits) */
-	u32 length;		/* Total RSDP length (incl. extended part) */
-	u64 xsdt_address;	/* Physical address of XSDT (64 bits) */
-	u8 ext_checksum;	/* Checksum of the whole table */
-	u8 reserved[3];
-};
-
-/* Generic ACPI header, provided by (almost) all tables */
-struct __packed acpi_table_header {
-	char signature[4];	/* ACPI signature (4 ASCII characters) */
-	u32 length;		/* Table length in bytes (incl. header) */
-	u8 revision;		/* Table version (not ACPI version!) */
-	volatile u8 checksum;	/* To make sum of entire table == 0 */
-	char oem_id[6];		/* OEM identification */
-	char oem_table_id[8];	/* OEM table identification */
-	u32 oem_revision;	/* OEM revision number */
-	char aslc_id[4];	/* ASL compiler vendor ID */
-	u32 aslc_revision;	/* ASL compiler revision number */
-};
-
-/* A maximum number of 32 ACPI tables ought to be enough for now */
-#define MAX_ACPI_TABLES		32
-
-/* RSDT (Root System Description Table) */
-struct acpi_rsdt {
-	struct acpi_table_header header;
-	u32 entry[MAX_ACPI_TABLES];
-};
-
-/* XSDT (Extended System Description Table) */
-struct acpi_xsdt {
-	struct acpi_table_header header;
-	u64 entry[MAX_ACPI_TABLES];
-};
-
-/* FADT Preferred Power Management Profile */
-enum acpi_pm_profile {
-	ACPI_PM_UNSPECIFIED = 0,
-	ACPI_PM_DESKTOP,
-	ACPI_PM_MOBILE,
-	ACPI_PM_WORKSTATION,
-	ACPI_PM_ENTERPRISE_SERVER,
-	ACPI_PM_SOHO_SERVER,
-	ACPI_PM_APPLIANCE_PC,
-	ACPI_PM_PERFORMANCE_SERVER,
-	ACPI_PM_TABLET
-};
-
-/* FADT flags for p_lvl2_lat and p_lvl3_lat */
-#define ACPI_FADT_C2_NOT_SUPPORTED	101
-#define ACPI_FADT_C3_NOT_SUPPORTED	1001
-
-/* FADT Boot Architecture Flags */
-#define ACPI_FADT_LEGACY_FREE		0x00
-#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
-#define ACPI_FADT_8042			(1 << 1)
-#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
-#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
-#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
-
-/* FADT Feature Flags */
-#define ACPI_FADT_WBINVD		(1 << 0)
-#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
-#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
-#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
-#define ACPI_FADT_POWER_BUTTON		(1 << 4)
-#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
-#define ACPI_FADT_FIXED_RTC		(1 << 6)
-#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
-#define ACPI_FADT_32BIT_TIMER		(1 << 8)
-#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
-#define ACPI_FADT_RESET_REGISTER	(1 << 10)
-#define ACPI_FADT_SEALED_CASE		(1 << 11)
-#define ACPI_FADT_HEADLESS		(1 << 12)
-#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
-#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
-#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
-#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
-#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
-#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
-#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
-#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
-#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
-
-enum acpi_address_space_type {
-	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
-	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
-	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
-	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
-	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
-	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
-	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
-};
-
-enum acpi_address_space_size {
-	ACPI_ACCESS_SIZE_UNDEFINED = 0,
-	ACPI_ACCESS_SIZE_BYTE_ACCESS,
-	ACPI_ACCESS_SIZE_WORD_ACCESS,
-	ACPI_ACCESS_SIZE_DWORD_ACCESS,
-	ACPI_ACCESS_SIZE_QWORD_ACCESS
-};
-
-struct acpi_gen_regaddr {
-	u8 space_id;	/* Address space ID */
-	u8 bit_width;	/* Register size in bits */
-	u8 bit_offset;	/* Register bit offset */
-	u8 access_size;	/* Access size */
-	u32 addrl;	/* Register address, low 32 bits */
-	u32 addrh;	/* Register address, high 32 bits */
-};
-
-/* FADT (Fixed ACPI Description Table) */
-struct __packed acpi_fadt {
-	struct acpi_table_header header;
-	u32 firmware_ctrl;
-	u32 dsdt;
-	u8 res1;
-	u8 preferred_pm_profile;
-	u16 sci_int;
-	u32 smi_cmd;
-	u8 acpi_enable;
-	u8 acpi_disable;
-	u8 s4bios_req;
-	u8 pstate_cnt;
-	u32 pm1a_evt_blk;
-	u32 pm1b_evt_blk;
-	u32 pm1a_cnt_blk;
-	u32 pm1b_cnt_blk;
-	u32 pm2_cnt_blk;
-	u32 pm_tmr_blk;
-	u32 gpe0_blk;
-	u32 gpe1_blk;
-	u8 pm1_evt_len;
-	u8 pm1_cnt_len;
-	u8 pm2_cnt_len;
-	u8 pm_tmr_len;
-	u8 gpe0_blk_len;
-	u8 gpe1_blk_len;
-	u8 gpe1_base;
-	u8 cst_cnt;
-	u16 p_lvl2_lat;
-	u16 p_lvl3_lat;
-	u16 flush_size;
-	u16 flush_stride;
-	u8 duty_offset;
-	u8 duty_width;
-	u8 day_alrm;
-	u8 mon_alrm;
-	u8 century;
-	u16 iapc_boot_arch;
-	u8 res2;
-	u32 flags;
-	struct acpi_gen_regaddr reset_reg;
-	u8 reset_value;
-	u16 arm_boot_arch;
-	u8 minor_revision;
-	u32 x_firmware_ctl_l;
-	u32 x_firmware_ctl_h;
-	u32 x_dsdt_l;
-	u32 x_dsdt_h;
-	struct acpi_gen_regaddr x_pm1a_evt_blk;
-	struct acpi_gen_regaddr x_pm1b_evt_blk;
-	struct acpi_gen_regaddr x_pm1a_cnt_blk;
-	struct acpi_gen_regaddr x_pm1b_cnt_blk;
-	struct acpi_gen_regaddr x_pm2_cnt_blk;
-	struct acpi_gen_regaddr x_pm_tmr_blk;
-	struct acpi_gen_regaddr x_gpe0_blk;
-	struct acpi_gen_regaddr x_gpe1_blk;
-};
-
-/* FACS flags */
-#define ACPI_FACS_S4BIOS_F	(1 << 0)
-#define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
-
-/* FACS (Firmware ACPI Control Structure) */
-struct acpi_facs {
-	char signature[4];		/* "FACS" */
-	u32 length;			/* Length in bytes (>= 64) */
-	u32 hardware_signature;		/* Hardware signature */
-	u32 firmware_waking_vector;	/* Firmware waking vector */
-	u32 global_lock;		/* Global lock */
-	u32 flags;			/* FACS flags */
-	u32 x_firmware_waking_vector_l;	/* X FW waking vector, low */
-	u32 x_firmware_waking_vector_h;	/* X FW waking vector, high */
-	u8 version;			/* Version 2 */
-	u8 res1[3];
-	u32 ospm_flags;			/* OSPM enabled flags */
-	u8 res2[24];
-};
-
-/* MADT flags */
-#define ACPI_MADT_PCAT_COMPAT	(1 << 0)
-
-/* MADT (Multiple APIC Description Table) */
-struct acpi_madt {
-	struct acpi_table_header header;
-	u32 lapic_addr;			/* Local APIC address */
-	u32 flags;			/* Multiple APIC flags */
-};
-
-/* MADT: APIC Structure Type*/
-enum acpi_apic_types {
-	ACPI_APIC_LAPIC	= 0,		/* Processor local APIC */
-	ACPI_APIC_IOAPIC,		/* I/O APIC */
-	ACPI_APIC_IRQ_SRC_OVERRIDE,	/* Interrupt source override */
-	ACPI_APIC_NMI_SRC,		/* NMI source */
-	ACPI_APIC_LAPIC_NMI,		/* Local APIC NMI */
-	ACPI_APIC_LAPIC_ADDR_OVERRIDE,	/* Local APIC address override */
-	ACPI_APIC_IOSAPIC,		/* I/O SAPIC */
-	ACPI_APIC_LSAPIC,		/* Local SAPIC */
-	ACPI_APIC_PLATFORM_IRQ_SRC,	/* Platform interrupt sources */
-	ACPI_APIC_LX2APIC,		/* Processor local x2APIC */
-	ACPI_APIC_LX2APIC_NMI,		/* Local x2APIC NMI */
-};
-
-/* MADT: Processor Local APIC Structure */
-
-#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
-
-struct acpi_madt_lapic {
-	u8 type;		/* Type (0) */
-	u8 length;		/* Length in bytes (8) */
-	u8 processor_id;	/* ACPI processor ID */
-	u8 apic_id;		/* Local APIC ID */
-	u32 flags;		/* Local APIC flags */
-};
-
-/* MADT: I/O APIC Structure */
-struct acpi_madt_ioapic {
-	u8 type;		/* Type (1) */
-	u8 length;		/* Length in bytes (12) */
-	u8 ioapic_id;		/* I/O APIC ID */
-	u8 reserved;
-	u32 ioapic_addr;	/* I/O APIC address */
-	u32 gsi_base;		/* Global system interrupt base */
-};
-
-/* MADT: Interrupt Source Override Structure */
-struct __packed acpi_madt_irqoverride {
-	u8 type;		/* Type (2) */
-	u8 length;		/* Length in bytes (10) */
-	u8 bus;			/* ISA (0) */
-	u8 source;		/* Bus-relative int. source (IRQ) */
-	u32 gsirq;		/* Global system interrupt */
-	u16 flags;		/* MPS INTI flags */
-};
-
-/* MADT: Local APIC NMI Structure */
-struct __packed acpi_madt_lapic_nmi {
-	u8 type;		/* Type (4) */
-	u8 length;		/* Length in bytes (6) */
-	u8 processor_id;	/* ACPI processor ID */
-	u16 flags;		/* MPS INTI flags */
-	u8 lint;		/* Local APIC LINT# */
-};
-
-/* MCFG (PCI Express MMIO config space BAR description table) */
-struct acpi_mcfg {
-	struct acpi_table_header header;
-	u8 reserved[8];
-};
-
-struct acpi_mcfg_mmconfig {
-	u32 base_address_l;
-	u32 base_address_h;
-	u16 pci_segment_group_number;
-	u8 start_bus_number;
-	u8 end_bus_number;
-	u8 reserved[4];
-};
-
-/* PM1_CNT bit defines */
-#define PM1_CNT_SCI_EN		(1 << 0)
-
-/* ACPI global NVS structure */
+struct acpi_facs;
+struct acpi_fadt;
 struct acpi_global_nvs;
-
-/* CSRT (Core System Resource Table) */
-struct acpi_csrt {
-	struct acpi_table_header header;
-};
-
-struct acpi_csrt_group {
-	u32 length;
-	u32 vendor_id;
-	u32 subvendor_id;
-	u16 device_id;
-	u16 subdevice_id;
-	u16 revision;
-	u16 reserved;
-	u32 shared_info_length;
-};
-
-struct acpi_csrt_shared_info {
-	u16 major_version;
-	u16 minor_version;
-	u32 mmio_base_low;
-	u32 mmio_base_high;
-	u32 gsi_interrupt;
-	u8 interrupt_polarity;
-	u8 interrupt_mode;
-	u8 num_channels;
-	u8 dma_address_width;
-	u16 base_request_line;
-	u16 num_handshake_signals;
-	u32 max_block_size;
-};
-
-/* DBG2 definitions are partially used for SPCR interface_type */
-
-/* Types for port_type field */
-
-#define ACPI_DBG2_SERIAL_PORT		0x8000
-#define ACPI_DBG2_1394_PORT		0x8001
-#define ACPI_DBG2_USB_PORT		0x8002
-#define ACPI_DBG2_NET_PORT		0x8003
-
-/* Subtypes for port_subtype field */
-
-#define ACPI_DBG2_16550_COMPATIBLE	0x0000
-#define ACPI_DBG2_16550_SUBSET		0x0001
-#define ACPI_DBG2_ARM_PL011		0x0003
-#define ACPI_DBG2_ARM_SBSA_32BIT	0x000D
-#define ACPI_DBG2_ARM_SBSA_GENERIC	0x000E
-#define ACPI_DBG2_ARM_DCC		0x000F
-#define ACPI_DBG2_BCM2835		0x0010
-
-#define ACPI_DBG2_1394_STANDARD		0x0000
-
-#define ACPI_DBG2_USB_XHCI		0x0000
-#define ACPI_DBG2_USB_EHCI		0x0001
-
-#define ACPI_DBG2_UNKNOWN		0x00FF
-
-/* SPCR (Serial Port Console Redirection table) */
-struct __packed acpi_spcr {
-	struct acpi_table_header header;
-	u8 interface_type;
-	u8 reserved[3];
-	struct acpi_gen_regaddr serial_port;
-	u8 interrupt_type;
-	u8 pc_interrupt;
-	u32 interrupt;		/* Global system interrupt */
-	u8 baud_rate;
-	u8 parity;
-	u8 stop_bits;
-	u8 flow_control;
-	u8 terminal_type;
-	u8 reserved1;
-	u16 pci_device_id;	/* Must be 0xffff if not PCI device */
-	u16 pci_vendor_id;	/* Must be 0xffff if not PCI device */
-	u8 pci_bus;
-	u8 pci_device;
-	u8 pci_function;
-	u32 pci_flags;
-	u8 pci_segment;
-	u32 reserved2;
-};
+struct acpi_madt_ioapic;
+struct acpi_madt_irqoverride;
+struct acpi_madt_lapic_nmi;
+struct acpi_mcfg_mmconfig;
+struct acpi_table_header;
 
 /* These can be used by the target port */
 
diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h
new file mode 100644
index 0000000000..fe62194b02
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2017 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ * Copyright Google LLC 2019
+ *
+ * Modified from coreboot apollolake/include/soc/nvs.h
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	/* Miscellaneous */
+	u8	pcnt; /* 0x00 - Processor Count */
+	u8	ppcm; /* 0x01 - Max PPC State */
+	u8	lids; /* 0x02 - LID State */
+	u8	pwrs; /* 0x03 - AC Power State */
+	u8	dpte; /* 0x04 - Enable DPTF */
+	u32	cbmc; /* 0x05 - 0x08 - U-Boot Console */
+	u64	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+	u64	gpei; /* 0x11 - 0x18 - GPE Wake Source */
+	u64	nhla; /* 0x19 - 0x20 - NHLT Address */
+	u32	nhll; /* 0x21 - 0x24 - NHLT Length */
+	u32	prt0; /* 0x25 - 0x28 - PERST_0 Address */
+	u8	scdp; /* 0x29 - SD_CD GPIO portid */
+	u8	scdo; /* 0x2a - GPIO pad offset relative to the community */
+	u8	uior; /* 0x2b - UART debug controller init on S3 resume */
+	u8	ecps; /* 0x2c - SGX Enabled status */
+	u64	emna; /* 0x2d - 0x34 EPC base address */
+	u64	elng; /* 0x35 - 0x3c EPC Length */
+	u8	unused1[0x100 - 0x3d];		/* Pad out to 256 bytes */
+	u8	unused2[0x1000 - 0x100];	/* Pad out to 4096 bytes */
+};
+
+#endif /* _GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h
index 9320afba56..85d42c02c4 100644
--- a/arch/x86/include/asm/arch-coreboot/timestamp.h
+++ b/arch/x86/include/asm/arch-coreboot/timestamp.h
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * This file is part of the coreboot project.
- *
  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * Taken from the coreboot version
  */
 
 #ifndef __COREBOOT_TIMESTAMP_H__
diff --git a/arch/x86/include/asm/intel_pinctrl_defs.h b/arch/x86/include/asm/intel_pinctrl_defs.h
index 6da06bb52b..1ea141f082 100644
--- a/arch/x86/include/asm/intel_pinctrl_defs.h
+++ b/arch/x86/include/asm/intel_pinctrl_defs.h
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * This file is part of the coreboot project.
- *
  * Copyright (C) 2015-2016 Intel Corp.
  * Copyright 2019 Google LLC
  *
diff --git a/arch/x86/lib/acpi.c b/arch/x86/lib/acpi.c
index cba9c24dd4..7431458dcf 100644
--- a/arch/x86/lib/acpi.c
+++ b/arch/x86/lib/acpi.c
@@ -4,7 +4,7 @@
  */
 
 #include <common.h>
-#include <asm/acpi_table.h>
+#include <acpi/acpi_table.h>
 #include <asm/io.h>
 #include <asm/tables.h>
 
diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c
index 197636c4b5..52410a515d 100644
--- a/arch/x86/lib/acpi_s3.c
+++ b/arch/x86/lib/acpi_s3.c
@@ -4,9 +4,9 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
+#include <acpi/acpi_s3.h>
+#include <acpi/acpi_table.h>
 #include <asm/acpi.h>
-#include <asm/acpi_table.h>
 #include <asm/post.h>
 #include <linux/linkage.h>
 
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 66e32f21bd..9346e165d8 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -12,8 +12,8 @@
 #include <dm/uclass-internal.h>
 #include <serial.h>
 #include <version.h>
+#include <acpi/acpi_table.h>
 #include <asm/acpi/global_nvs.h>
-#include <asm/acpi_table.h>
 #include <asm/ioapic.h>
 #include <asm/lapic.h>
 #include <asm/mpspec.h>
@@ -471,6 +471,15 @@ static void acpi_create_spcr(struct acpi_spcr *spcr)
 	spcr->pci_device_id = 0xffff;
 	spcr->pci_vendor_id = 0xffff;
 
+	/*
+	 * SPCR has no clue if the UART base clock speed is different
+	 * to the default one. However, the SPCR 1.04 defines baud rate
+	 * 0 as a preconfigured state of UART and OS is supposed not
+	 * to touch the configuration of the serial device.
+	 */
+	if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
+		spcr->baud_rate = 0;
+
 	/* Fix checksum */
 	header->checksum = table_compute_checksum((void *)spcr, header->length);
 }
diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c
index 2943e11d2a..c996fc588d 100644
--- a/arch/x86/lib/coreboot_table.c
+++ b/arch/x86/lib/coreboot_table.c
@@ -4,9 +4,9 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <malloc.h>
 #include <vbe.h>
+#include <acpi/acpi_s3.h>
 #include <asm/coreboot_tables.h>
 #include <asm/e820.h>
 
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 5eff0f99aa..267527eb34 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -4,11 +4,11 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <cpu_func.h>
 #include <dm.h>
 #include <errno.h>
 #include <rtc.h>
+#include <acpi/acpi_s3.h>
 #include <asm/cmos_layout.h>
 #include <asm/early_cmos.h>
 #include <asm/io.h>
diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c
index aee2a05044..0a726807c2 100644
--- a/arch/x86/lib/fsp1/fsp_common.c
+++ b/arch/x86/lib/fsp1/fsp_common.c
@@ -4,11 +4,11 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <rtc.h>
+#include <acpi/acpi_s3.h>
 #include <asm/cmos_layout.h>
 #include <asm/early_cmos.h>
 #include <asm/io.h>
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index 90a238a224..c8f2c09b6a 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -5,9 +5,9 @@
  */
 
 #include <common.h>
-#include <acpi_s3.h>
 #include <handoff.h>
 #include <spl.h>
+#include <acpi/acpi_s3.h>
 #include <asm/arch/cpu.h>
 #include <asm/fsp/fsp_support.h>
 #include <asm/fsp2/fsp_api.h>
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 7aea722d0b..574d331d76 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -6,10 +6,10 @@
 #include <common.h>
 #include <malloc.h>
 #include <smbios.h>
+#include <acpi/acpi_table.h>
 #include <asm/sfi.h>
 #include <asm/mpspec.h>
 #include <asm/tables.h>
-#include <asm/acpi_table.h>
 #include <asm/coreboot_tables.h>
 
 /**
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 9b5e767ccc..ffc09630b7 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -16,7 +16,7 @@
 #include <env.h>
 #include <irq_func.h>
 #include <malloc.h>
-#include <asm/acpi_table.h>
+#include <acpi/acpi_table.h>
 #include <asm/io.h>
 #include <asm/ptrace.h>
 #include <asm/zimage.h>