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| author | Tom Rini <trini@konsulko.com> | 2019-12-18 07:20:19 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-12-18 07:20:19 -0500 |
| commit | c0912f9bbfb26dd03d189953678691b799d35b6e (patch) | |
| tree | f879600cd26b8d4678a174854b623941e5dc2ada /arch/x86/include/asm/lpss.h | |
| parent | 533c9f5714bdba79dc6f2629284d4c1a08a611d1 (diff) | |
| parent | a1d6dc3f84071f05574044f337dbdca70fae495d (diff) | |
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
Diffstat (limited to 'arch/x86/include/asm/lpss.h')
| -rw-r--r-- | arch/x86/include/asm/lpss.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/x86/include/asm/lpss.h b/arch/x86/include/asm/lpss.h new file mode 100644 index 0000000000..7814872688 --- /dev/null +++ b/arch/x86/include/asm/lpss.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __ASM_LPSS_H +#define __ASM_LPSS_H + +struct udevice; + +/* D0 and D3 enable config */ +enum lpss_pwr_state { + STATE_D0 = 0, + STATE_D3 = 3 +}; + +/** + * lpss_reset_release() - Release device from reset + * + * This is used for devices which have LPSS support. + * + * @regs: Pointer to device registers + */ +void lpss_reset_release(void *regs); + +/** + * lpss_set_power_state() - Change power state of a device + * + * This is used for devices which have LPSS support. + * + * @dev: Device to update + * @state: New power state to set + */ +void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state); + +#endif |