diff options
author | Tom Rini <trini@konsulko.com> | 2019-12-18 07:20:19 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2019-12-18 07:20:19 -0500 |
commit | c0912f9bbfb26dd03d189953678691b799d35b6e (patch) | |
tree | f879600cd26b8d4678a174854b623941e5dc2ada /arch/x86/include/asm/fsp2/fsp_api.h | |
parent | 533c9f5714bdba79dc6f2629284d4c1a08a611d1 (diff) | |
parent | a1d6dc3f84071f05574044f337dbdca70fae495d (diff) |
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
Diffstat (limited to 'arch/x86/include/asm/fsp2/fsp_api.h')
-rw-r--r-- | arch/x86/include/asm/fsp2/fsp_api.h | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/x86/include/asm/fsp2/fsp_api.h b/arch/x86/include/asm/fsp2/fsp_api.h new file mode 100644 index 0000000000..af1e8857b9 --- /dev/null +++ b/arch/x86/include/asm/fsp2/fsp_api.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) + * Mostly taken from coreboot fsp2_0/memory_init.c + */ + +#ifndef __ASM_FSP2_API_H +#define __ASM_FSP2_API_H + +#include <asm/fsp/fsp_api.h> + +struct fspm_upd; +struct fsps_upd; +struct hob_header; + +enum fsp_boot_mode { + FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00, + FSP_BOOT_WITH_MINIMAL_CONFIGURATION = 0x01, + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES = 0x02, + FSP_BOOT_ON_S4_RESUME = 0x05, + FSP_BOOT_ON_S3_RESUME = 0x11, + FSP_BOOT_ON_FLASH_UPDATE = 0x12, + FSP_BOOT_IN_RECOVERY_MODE = 0x20 +}; + +struct __packed fsp_upd_header { + u64 signature; + u8 revision; + u8 reserved[23]; +}; + +/** + * fsp_memory_init() - Init the SDRAM + * + * @s3wake: true if we are booting from resume, so cannot reinit the mememory + * from scatch since we will lose its contents + * @use_spi_flash: true to use the fast SPI driver to read FSP, otherwise use + * mapped SPI + * @return 0 if OK, -ve on error + */ +int fsp_memory_init(bool s3wake, bool use_spi_flash); + +typedef asmlinkage int (*fsp_memory_init_func)(struct fspm_upd *params, + struct hob_header **hobp); + +/** + * fsp_silicon_init() - Init the silicon + * + * This calls the FSP's 'silicon init' entry point + * + * @s3wake: true if we are booting from resume, so cannot reinit the mememory + * from scatch since we will lose its contents + * @use_spi_flash: true to use the fast SPI driver to read FSP, otherwise use + * mapped SPI + * @return 0 if OK, -ve on error + */ +int fsp_silicon_init(bool s3wake, bool use_spi_flash); + +typedef asmlinkage int (*fsp_silicon_init_func)(struct fsps_upd *params); + +#endif |